ITC 2016 Tutorials
ITC 2016 offers 12 tutorials, taught by leading experts, over two days. Catch up on the latest in an area with advanced tutorials or learn the basics. Tutorial titles appear below. Watch this space for more details as they become available.
|Sunday Morning, November 13||Sunday Afternoon, November 13|
|TUTORIAL 1: Testing of TSV-Based 2.5D- AND 3D-Stacked ICs||Erik Jan MARINISSEN, Krishnendu CHAKRABARTY||TUTORIAL 4: Testing of Automotive IC’s: Introduction and Advances||Davide APPELLO, Oscar BALLAN, Ernesto SANCHEZ|
|TUTORIAL 2: Delay Test: Concepts, Theory and Recent Trends||Haralampos STRATIGOPOULOS, Yiorgos MAKRIS||TUTORIAL 5: Diagnosis Driven Yield Analysis||Wu-Tung CHENG, Wu YANG, Yu HUANG|
|TUTORIAL 3: Test Opportunities and Challenges for Secure Hardware and Verifying Trust in Integrated Circuits||Domenic FORTE, Mohammad TEHRANIPOOR||TUTORIAL 6: Understanding the Unique Fallout from Cell Aware Tests||Adit SINGH|
|Monday Morning, November 14||Monday Afternoon, November 14|
|TUTORIAL 7: Memory Test & Repair in FinFET Era||Yervant ZORIAN||TUTORIAL 10: Automotive Reliability & Test Strategies||Yervant ZORIAN|
|TUTORIAL 8: Test, Diagnosis, And Root-Cause Identification of Failures for Boards and Systems||Krishnendu CHAKRABARTY, William EKLOW||TUTORIAL 11: Combining structural and functional test approaches across system levels||Artur JUTMAN, Hans-Joachim WUNDERLICH, Matteo SONZA REORDA|
|TUTORIAL 9: Mixed-Signal DFT & BIST: Trends, Principles, and Solutions||Steve SUNTER||TUTORIAL 12: Practices in High Speed I/O Testing||Salem ABDENNADHER, Saghir SHAIKH|
- Testing of TSV-Based 2.5D- AND 3D-Stacked ICs
EJ. Marinissen, K. Chakrabarty
Stacked ICs with vertical interconnects containing fine-pitch micro- bumps and through-silicon vias (TSVs) are a hot-topic in design and manufacturing communities. These 2.5D- and 3D-SICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, increased yield and decreased product cost. This tutorial presents key concepts in 3D technology, terminology, and benefits. We discuss design, test challenges and emerging solutions for 2.5D- and 3D-SICs. Covered topics include overview of 3D integration and trend-setting products such as 2.5D-FPGA, 3D-stacked memory chips, test flows and test content for 3D chips, advanced wafer probing, 3D design-for-test architectures and ongoing IEEE P1838 standardization, and 3D test cost modeling and test-flow selection.
Intended Audience:Test and design-for-test engineers and their managers; researchers, university professors and students; test methodology developers; test-automation tool developers.
- From Data to Actions: Applications of Data Analytics to Semiconductor Manufacture and Test
H. Stratigopoulos, Y. Makris
This tutorial seeks to elucidate the utility of data analytics in semiconductor manufacturing and test. Relevant concepts from data analytics theory will be introduced and agglomerated with current practice, showcasing effectiveness on actual case studies with industrial data. A comprehensive survey of the relevant literature will be provided, organized around four themes: (i) Test cost reduction through replacement of expensive tests by inexpensive alternatives and/or elimination of superfluous, either statically or adaptively during application, (ii) Pre- deployment evaluation of candidate test methods through probabilistic test metrics, (iii) Post- production performance calibration through cost- effective knob tuning, and (iv) Yield learning and process monitoring through analysis of process variation impact on wafer-level spatial correlation
Intended Audience:This tutorial is intended for (i) process and test engineers who wish to understand the utility of data analytics in their practice, (ii) graduate students/faculty/researchers who wish to familiarize with the state-of-the-art and conduct research in this domain, and (iii) data analytics experts who wish to apply their expertise on semiconductor manufacturing data.
- Test Opportunities and Challenges for Secure Hardware and Verifying Trust in Integrated Circuits
D. Forte, M. Tehranipoor
The migration from a vertical to horizontal business model has made it easier to introduce vulnerabilities to electronic component design and supply chain. This tutorial discusses the major issues including securing hardware, verifying trustworthiness of ICs, unique key generation, side-channel attacks and will place emphasis on detection/prevention of hardware Trojans and counterfeit electronic parts and how test can help. (i) Introduction to hardware security and trust (physically unclonable functions, true random number generation, hardware Trojans, counterfeit ICs, side-channel attacks, supply chain vulnerabilities), (ii) Background and motivation for hardware Trojan and counterfeit prevention/detection; (iii) Taxonomies related to both topics; (iv) Existing solutions; (v) Open test challenges; (vi) Design for security and trust, (vii) New and unified solutions.
Intended Audience: This tutorial is perfect for either those who are beginners or those who have been involved in hardware security for several years. For beginners, we shall provide extensive motivation and background hardware security and trust. For the more experienced, we will discuss an up-to-date understanding of existing solutions, the challenges still unaddressed, and the role test and design for security plays in securing modern designs.
- Testing of Automotive ICs: Introduction and Advances
D. Appello, O. Ballan, E. Sanchez
Electronics content in the car is constantly growing. On top of traditional applications for engine control, transmission, braking/steering, passive safety, body and dashboard also multimedia, advanced driver assistance and car2X segments are rapidly growing. The stability and extended duration in manufacturing of these components makes them very attractive for the industry. Extreme product quality achieved with very low cost is the key challenge. The proposed tutorial covers a broad range of topics which are defining the testability, testing and manufacturing requirements of automotive products. Advanced topics like testing of safety critical and secure devices are proposed beside more traditional topics like testability, test development, qualification, industrialization, burn-in and manufacturing. Relevant industrial cases will be proposed to participants.
Intended Audience: Test and product engineers, designers and DFT engineers, quality engineers, student and researchers in the area of test and testability
- Diagnosis-driven Yield Analysis
W-T. Cheng, W. Yang, Y. Huang
Delivering a stable high-yield product on time is the ultimate goal for the semiconductor industry. Reaching this goal becomes more and more difficult, especially when cell internal defects become prevalent. The main challenges in the yield analysis process are to identify the systematic issues, find their root causes and select associated devices with the identified systematic defects for further validation by physical failure analysis. This tutorial discusses the methodologies that improve yield of digital semiconductor devices through scan-based test, volume diagnosis and diagnosis-driven yield analysis (DDYA). This gives engineers who work on yield improvement a very fast and highly effective way of defect localization and identification, complementing their traditional and hardware-based methods.
Intended Audience: Engineers and managers responsible for design, test, quality or yield of a product; Engineers and managers responsible for product engineering and technology bring-up; Failure analysis lab engineers & managers; Engineers involved in manufacturing production or process development; Anyone involved with the financial impact of low yield or low product quality.
- Targeting “Zero Defect” IC Quality: Advanced Cell-Aware Fault Models and Adaptive Test
Commercial applications continue to demand ever higher IC quality, most notably a “zero defect” target from automotive manufacturers. However, recent experience with new Cell Aware Tests suggests that current structural tests can miss significant defectivity. This two-part tutorial presents a detailed study of the state-of-the-art techniques directed at targeting “Zero-Defect” IC quality. In part one we explain new fault models, including the Cell Aware methodology, for an in-depth understanding of the actual defects in modern standard cells that are missed by stuck-at and TDF tests but detected by the new tests. Part two introduces innovative statistical adaptive techniques that improve test effectiveness by optimizing the test applied to individual parts.
Intended Audience: Test researchers and academics, DFT managers and engineers, EDA test/DFT tool developers, test and reliability managers and engineers, automotive electronics managers and engineers.
- Memory Test and Repair in the FinFET Era
Recent growth in content creation has led to an explosion in the use of embedded memories. This tutorial will present the trends and challenges of growing memory content on chip and how to ensure detection of today’s defects upon manufacturing and during life time, including process variation and FinFET- specific defects reaching 7-nm level. BISTand repair solutions to address yield optimization, endurance and data retention of failure modes will be presented. Given the tens of thousands of embedded memory instances in today’s SOCs, the tutorial will also cover power management constraints, functional timing implications, test scheduling optimization and area minimization options.
Intended Audience: DFT, Test and Reliability Engineers, Engineering Managers, Reliability and Quality Assurance Managers, Researchers and Research Students.
- Test, Diagnosis and Root-Cause Identification of Failures for Boards and Systems
K. Chakrabarty, W. Eklow
The gap between working silicon and a working board/system is becoming more significant and problematic as technology scales and complexity grows. The result of this increasing gap is failures at the board and system level that cannot be duplicated at the component level. These failures are most often referred to as “NTFs” (No Trouble Founds). The result of these NTFs can range from higher manufacturing costs and inventories to failure to get the product out of the door. This tutorial provides a detailed background on the nature of this problem and will provide DFT, test, and root-cause identification solutions at board/system level. Practical insights from industry case studies will be highlighted, and recent research from academia can help solving these problems.
Intended Audience: Board/System designers, Board/system test engineers and their managers, researchers, test methodology developers, and test tool developers.
- Mixed-Signal DFT and BIST: Trends, Principles and Solutions
We analyze recent trends in IC processes and design, and implications for test, then look at trends in testing. Next, we discuss trends in ad hoc DFT and fault simulation, then all relevant IEEE DFT standards: 1149.1, .4, .6, .7, .8, P1149.10 and 1687. The trend analysis concludes with a review of BIST techniques. Addressed circuits include PLL/DLL,ADC/DAC, SerDes/DDR, general I/Os and last, but not least, random analog. Next, seven essential principles of practical analog BIST are presented. Lastly, we discuss practical DFT techniques, ranging from analog defect simulation and the classic analog bus, to oversampling and undersampling methods that greatly improve range, resolution and reusability.
Intended Audience: Designers, DFT engineers, test engineers, and managers responsible for analog/mixed-signal/HSIOfunctions in SoCs
- Automotive Reliability and Test Strategies
R. Mariani, N. Nandra Y. Zorian
Given the fast-growing automotive semiconductor industry, this tutorial will discuss the implications of automotive test, reliability and functional safety requirements on all aspects of the SOC lifecycle: design, silicon bring up, volume production and, particularly, in the field test. Automotive safety-critical chips that need multiple field test strategies, such as power-on self-test, periodic in-system self-test and error correction will also be covered. The tutorial will discuss how incorporating self-test and repair infrastructure with high-efficiency capabilities can help minimize the impact on power, performance and area, while addressing the need for less than 10 DPPM. The benefits of selecting an ISO 26262-certified IP to ensure functional safety requirements, while accelerating time to market for SOCs.
Intended Audience:DFT, test, reliability, and functional safety engineers, engineering managers, reliability and quality assurance managers, researchers and research students.
- Combining Structural and Functional Test Approaches Across System Levels
A. Jutman, H-J. Wunderlich
This tutorial introduces into the best practices, current challenges and advanced techniques of high-quality system-level test and diagnosis. Specialized techniques and industrial standards of testing complex systems (which may correspond to a system-on-chip, board or interconnected system) are introduced. The reuse for system test of design-for-test structures and test data developed at module level is discussed, including the limitations and research challenges. Structural test methods have to be complemented by functional methods; hence, state-of-the-art and leading edge research for functional testing are covered. Solutions change depending on the scenario (manufacturing test or in-field test) and the goal (test or diagnosis). The tutorial also discusses the role of standards and regulations in the area.
Intended Audience: Professionals from IC-level and board-level domains who want to extend their horizon in the complementary test domain learning best practices across the levels and technologies in the areas of board and IC testing, structural and functional test, test at the end of manufacturing and in the field.
- Practices in High-Speed I/O Testing
S. Abdennadher, S. Shaikh
This tutorial presents the existing industrial techniques to meet the ever- increasing test complexity of high-speed IO’s (HSIO). It first describes the basic design of both serial and parallel HSIOs, and then presents various testing methods ofHSIO, such as timing margining, voltage margining, compensation testing, leakage testing, etc. The examples of all these test methods will be presented with special emphasis on DFT and BIST-based approaches of HSIO testing and their suitability to the production-level environment.
Intended Audience: This tutorial is most suitable for design, test and DFT engineers involved in actual implementation of high- speed I/O-based systems. The architects and engineering managers would also greatly benefit from this tutorial.