Plenary Keynote  (Tues Sept 27)

Parthasarathy Ranganathan

VP/technical Fellow, Google

Make computing count: some grand opportunities for testing

Biography:  Partha Ranganathan is currently a VP, technical Fellow at Google where he is the area technical lead for hardware and datacenters, designing systems at scale. Prior to this, he was a HP Fellow and Chief Technologist at Hewlett Packard Labs where he led their research on systems and data centers.

Partha has worked on several interdisciplinary systems projects with broad impact on both academia and industry, including widely-used innovations in energy-aware user interfaces, heterogeneous multi-cores, power-efficient servers, accelerators, and disaggregated and data-centric data centers. He has published extensively (including being the co-author on the popular “Datacenter as a Computer” textbook), is a co-inventor on more than 100 patents, and has been recognized with numerous awards. He has been named a top-15 enterprise technology rock star by Business Insider, one of the top 35 young innovators in the world by MIT Tech Review, and is a recipient of the ACM SIGARCH Maurice Wilkes award, Rice University’s Outstanding Young Engineering Alumni award, and the IIT Madras distinguished alumni award. He is also a Fellow of the IEEE and ACM, and is currently on the board of directors for OpenCompute.

Abstract: TBD


Wednesday Keynote


John Shaft

Lawrence Berkeley National Labs

The future of High Performance Computing Beyond Moore’s Law

Biography:  John Shalf is Department Head for Computer Science at Lawrence Berkeley National Laboratory, and recently was deputy director of Hardware Technology for the DOE Exascale Computing Project.

Shalf is a coauthor of over 80 publications in the field of parallel computing software and HPC technology, including three best papers and the widely cited report “The Landscape of Parallel Computing Research: A View from Berkeley” (with David Patterson and others). He also coauthored the 2008 “ExaScale Software Study: Software Challenges in Extreme Scale Systems,” which set the Defense Advanced Research Project Agency’s (DARPA’s) information technology research investment strategy. Prior to coming to Berkeley Laboratory, John worked at the National Center for Supercomputing Applications and the Max Planck Institute for Gravitation Physics/Albert Einstein Institute (AEI) where he was was co-creator of the Cactus Computational Toolkit.

Abstract: TBD.

 


Thursday Keynote

Grady Giles, Mike Bienek, & Tim Wood

AMD

What did we learn in 120 years of DFT and test? 

Biography:  Grady Giles, Mike Bienek, and Tim Wood are all members of the DFX team at AMD, with a combined 120+ years of experience in the industry.

Grady worked at TI and Motorola prior to joining AMD, Mike worked at Convex, MegaTest, Geocast, and Neofocal prior to AMD, and Tim has been at AMD for his entire career.  Collectively they have been responsible for dozens of patents, many ITC papers (including two Best Paper awards), heavy involvement with IEEE standards and the Semiconductor Research Consortium, SWDFT and ITC conference program committees, and extensive engagements over many years across the industry.  Grady has been a champion of robust scan-based testability measures for decades, Mike architected methodologies and tools to achieve Known Good Die for complex supercomputer assemblies, and Tim led the DFT efforts for many generations of cutting-edge microprocessors.  Grady and Mike are both graduates of Texas A&M, and Tim earned his degree from Rensselaer Polytechnic Institute.

Abstract: TBD

 


Visionary Talk (day TBD)

Tim Cheng

The Hong Kong University of Science and Technology

Ultra Low-Power AI Accelerators for AIoT –
Compute-in-memory, Co-Design, and Heterogeneous Integration

 

Biography: Tim Cheng is currently Vice-President for Research and Development at Hong Kong University of Science and Technology (HKUST) and Chair Professor jointly in the Departments of ECE and CSE.

His current research interests include design, EDA, computer vision, and medical image analysis. In 2020, he received HK$443.9M funding to lead the founding of the AI Chip Center for Emerging Smart Systems (ACCESS) which is a multidisciplinary center aims to advance IC design and EDA to help realize ubiquitous AI applications in society.He received his PhD from University of California, Berkeley. Prior to joining HKUST, he was a Professor at the University of California, Santa Barbara, and spent five years at AT&T Bell Laboratories. At UCSB, Cheng served as Founding Director of the Computer Engineering Program (1999-2002), Chair of ECE Department (2005-2008), and Associate Vice-Chancellor for Research (2013-2016). At HKUST, Cheng served as Dean of Engineering (2016-March 2022) prior to taking the VPRD role.Cheng, an IEEE fellow and a fellow of Hong Kong Academy of Engineering Sciences a, received 12 Best Paper Awards from various IEEE and ACM conferences and journals. He has also received UCSB College of Engineering Outstanding Teaching Faculty Award, Pan Wen Yuan Outstanding Research Award, 2020,  and Fellow of School of Engineering, The University of Tokyo. He served as Editor-in-Chief of IEEE Design and Test of Computers and was a board member of IEEE Council of Electronic Design Automation’s Board of Governors and IEEE Computer Society’s Publication Board.

Abstract:  We will give an overview of the objectives and some recent progress in designing ultra low-power AI accelerators for supporting a wide range of AIoT devices with powerful embedded intelligence. Specifically, we will discuss the roles of emerging memory and compute-in-memory for data-centric computing, application-specific co-design framework supporting light-weight deep learning which integrates neural network (NN) search, hardware-friendly NN compression and NN-aware architecture design for iterative co-optimization, as well as the critical role of 3D integration of processors and memory arrays for power, performance and size.