ITC keynotes have been one of the most valuable parts of the conference, leading to our decision to triple them for the 50th anniversary. We have six keynote speakers who will focus on a spectrum of advances in our ecosystem. We will have executives from advanced semiconductor and systems companies, government agencies and academia.
A NEW feature at ITC 50 will be our Visionary Talks, delivered by prominent executives from our EDA and test equipment and yield optimization companies, which will be held during the same plenary sessions as the keynotes.
Mike Campbell, Senior Vice President of Engineering, Qualcomm
A new era for Test and test complexity
Michael Campbell is Senior Vice President of Engineering for QUALCOMM CDMA Technologies, responsible for QCT Product and Test, Test Automation, Failure Analysis and yield. Mike joined QCT in 1996 and since then Mike has led multiple teams including, FA, Quality, Design Automation, Yield optimization, Product Engineering, Test Engineering, and Foundry semiconductor analysis.
While at Qualcomm, Mike has helped bring up and drive the design office in Bangalore, Design and Test development center in Singapore and a development facility in Taiwan. In his current role, he is working to improve / stream all processes impacting TTM, new process node enablement, and revolutionize PTE tasks by driving machine learning as a 21st century requirement for all facets of PTE and Yield engineering work.
Prior to joining QUALCOMM, Mike was with other companies, including Mostek, INMOS and Honeywell. He holds a BSEE & CE from Clarkson University.
Morning Visionary talk
Since co-founding Synopsys in 1986, Dr. de Geus has expanded Synopsys from a start-up synthesis company to a global high-tech leader. Long considered a pioneer in our industry, he’s been recognized for his technical, business and community achievements with multiple awards and honors, including: Electronic Business Magazine’s “CEO of the Year”, the IEEE Robert N. Noyce Medal, Phil Kaufman Award for distinguished contributions to EDA, the GSA Morris Chang Exemplary Leadership Award, the Silicon Valley Engineering Council Hall of Fame Award, and the SVLG Lifetime Achievement Award, National Academy of Engineering, Foreign Member. He serves on the Boards of the Silicon Valley Leadership Group, Applied Materials, the Global Semiconductor Alliance, and the Electronic System Design Alliance.
Serge Leef joined DARPA in August 2018 as a program manager in the Microsystems Technology Office (MTO). His research interests include computer architecture, simulation, synthesis, semiconductor intellectual property (IP), cyber-physical modeling, distributed systems, secure design flows, and supply chain management. He is also interested in the facilitation of startup ecosystems and business aspects of technology. Leef came to DARPA from Mentor, a Siemens Business where from 2010 until 2018 he was a Vice President of New Ventures, responsible for identifying and developing technology and business opportunities in systems-oriented markets. Prior to joining Mentor, he was responsible for design automation at Silicon Graphics. He also managed a CAE/CAD organization at Microchip and developed functional and physical design and verification tools for major 8- and 16-bit microcontroller and microprocessor programs at Intel.
Leef received his Bachelor of Science degree in electrical engineering and Master of Science degree in computer science from Arizona State University. He has served on corporate, state, and academic advisory boards, delivered numerous public speeches, and holds two patents
Afternoon Visionary talk
John Kibarian, President & CEO, PDF Solutions
“The Outlook for Manufacturing Test in a Future Driven by Big Data Analytics and the IIoT”
John Kibarian is the CEO, president, and co-founder of PDF Solutions. Before founding the company in 1991, Dr. Kibarian was a researcher at Carnegie Mellon University’s SEMATECH Center for Rapid Yield Learning. At CMU, John developed algorithms for diagnosing process variations based on electrical test data and for achieving yield maximization based on circuit optimization and statistical simulation of processes and devices. Kibarian holds B.S. and M.S. degrees in Electrical Engineering and a Ph.D. in Computer Engineering, all from Carnegie Mellon University.
Kevork Kechichian joined NXP semiconductors in April 2019 as Senior Vice President of MCU/MPU Engineering, leading global teams in architecture, IP and SoC, targeting diverse markets in automotive microcontrollers and processors, media processers, industrial IoT and networking. Prior to NXP, Kevork held the role of SVP Engineering at Qualcomm, managing the global Snapdragon SoC teams.
Kevork’s career spans 25+ years in various SoC engineering and leadership roles – ATI Technologies, PMC-Sierra, Silicon Optix and LSI. He holds a bachelor’s degree in Electrical Engineering from American University of Beirut in Lebanon, and a master’s degree in Electrical Engineering from Concordia University in Montreal, Canada.
Morning Visionary talk
Joseph Sawicki, Executive Vice President, Mentor IC EDA, Mentor, a Siemens Business
Moving from Production Test to Life Cycle Management Mile
Joseph Sawicki is a leading expert in IC nanometer design and manufacturing challenges. Formerly responsible for Mentor’s industry-leading design-to-silicon products, including the Calibre physical verification and DFM platform and Mentor’s Tessent design-for-test product line, Sawicki now oversees all business units in the Mentor IC segment.
Sawicki joined Mentor Graphics in 1990 and has held previous positions in applications engineering, sales, marketing and management. He holds a BSEE from the University of Rochester, an MBA from Northeastern University’s High Technology Program, and has completed the Harvard Business School Advanced Management Program.
Leon Stok is Vice President of IBM’s Electronic Design Automation group. His team delivers world-class design and verification flows and tools being used to design the world’s largest supercomputers, IBM systemZ and Power systems. Prior to this he held positions as director of EDA and executive assistant to IBM’s Senior Vice President of Technology and Intellectual Property and executive assistant to IBM’s Senior Vice President of the Technology group. Leon Stok studied electrical engineering at Eindhoven University of Technology, the Netherlands, from which he graduated with honors in 1986. He obtained a Ph.D. degree from Eindhoven University in 1991. At IBM’s Thomas J. Watson Research Center, Leon Stok pioneered logic synthesis, as part of the team that developed BooleDozer. Dr. Stok has published over sixty papers on many aspects of high level, architectural and logic synthesis, low power design, placement driven synthesis and on the automatic placement and routing for schematic diagrams. He holds 13 patents in EDA. He was elected an IEEE fellow for the development and application of high-level and logic synthesis algorithms.
Giovanni de Micheli, Director IEE Center, EPFL
“Democratic circuits for a safer and greener tomorrow”
Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering at EPFL Lausanne, Switzerland. He is a Fellow of ACM and IEEE, a member of the Academia Europaea and an International Honorary member of the American Academy of Arts and Sciences. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration.
Prof. De Micheli is the recipient of the 2016 IEEE/CS Harry Goode award for seminal contributions to design and design tools of Networks on Chips, the 2016 EDAA Lifetime Achievement Award, the 2012 IEEE/CAS Mac Van Valkenburg award and other awards. He has been served IEEE in several capacities, namely: Division 1 Director (2008-9), co-founder and President Elect of the IEEE Council on EDA (2005-7), President of the IEEE CAS Society (2003), and chair of the Design-Automation Conference-DAC (2000).
Morning Visionary talk
Gregory Smith, President, Semiconductor Test Division, Teradyne Inc.
“How Semiconductor Complexity Drives ATE Architecture”
Mr. Smith joined Teradyne in 2006 as a semiconductor test product manager. He has served in a variety of roles at Teradyne including Manager of the Complex SOC Business Unit, and Vice President of SOC Marketing in the Semiconductor Test Division.
Mr. Smith has over 30 years of engineering, management and marketing experience in semiconductor test.
Mr. Smith earned a Bachelor’s degree in Electrical Engineering from the University of Pennsylvania.
Andreas Aal, Semi Strategy & Reliability, VW AG
“The impact of functional safety and cyber security assurance on the role of testing for autonomous vehicle electrical system designs”
Andreas Aal (SM) drives the semiconductor strategy and reliability assurance activities within the electric-/electronic development department at Volkswagen, Germany, which he joint 2011. His activities concentrate on technology capability enhancement (component construction & system architecture) of most advanced nodes as well as optimization of power electronics integration for automotive applications. Andreas is a member of the IEEE Electron Devices, CPMT, Nuclear and Plasma Sciences, Reliability and Solid-State Circuits Societies and also a frequent participant / contributor of the JEDEC subcommittee 14.2. Since 2007 he is chair of the German VDE ITG group MN 5.6 on (f)WLR, reliability simulations and qualification.
Afternoon Visionary talk
Mr Schaub has worked in the semiconductor industry for 25 years. He authored, Production Testing of RF and System-on-a-Chip Devices for Wireless Communications. Keith Founded and exited several start-ups. Mr Schaub consulted on RF system architectures for several fortune 500 companies. Mr Schaub has multiple AI related patents & papers – NLP & VR for enhance test engineering debug, Smart Auto RF matching load board, Automated/Robotics Smartphone production testing, AI/ML for anomolous defect classification.