Here is a summary of five of the special sessions available in the 2022 ITC program (stay tuned for more information on others)

In-memory Computing

Hardware Security Certificate

Quantum Circuit Testing

High-power Electronics

ITC Asia papers

In-Memory Computing Design and Test challenges


  • Saman Adham, TSMC, North America, USA,

Saman Adham is a Senior Manager at TSMC North America, in Austin Texas.

He received a BS and MS in Electrical Engineering from the University of Baghdad, Iraq, in 1977 and 1979 respectively and his PhD from Queens University, Canada in 1991. Dr. Adham has over 32 years of industrial experience with a proven track record in the area of design for test (DFT) and built-in self-test. He joined Nortel Networks in 1991 and then became the DFT advisor of Nortel Networks, developing design for test methodologies and built-in self-test. From 1999 to 2009, Dr. Adham was the Director of Engineering at LogicVision Inc. He joined TSMC Ottawa, Canada in 2009 as Senior Manager, BIST and ASIC design group and recently moved to TSMC North America in Austin, Texas.  Dr. Adham has a considerable publication record in the area of design for test and built-in self-test. He also holds more than 50 US patents and several pending patents. He is the chair of IEEE Std 1450.6.2 working group, standardizing memory test modeling. Additionally, he is a reviewer for many DFT/BIST, hardware security journals and conferences.
  • Second organizer: Said Hamdioui, Delft University,

Said Hamdioui is Professor on Dependable and Emerging Computer Technologies and Head of the Computer Engineering Laboratory at Delft University of Technology (TUDelft).

Prior to joining TUDelft, he worked for Intel, Philips Semiconductors and NXP Semiconductors. His research focuses on two domains: Dependable CMOS nano-computing (including Reliability, Testability, Hardware Security) and emerging technologies and computing paradigms.Hamdioui owns two patents, has published/contributed to three books, and has authored over 250 publications in major journals and conference proceedings. He was/is on the editor board of many journals (TVLSI, JETTA, D&T, JETC, etc), and has received many best paper awards/nominations at leading conference (ITC, ETS, DATE, ICCD, ISVLIS, etc.). Hamdioui has presented many tutorials about memory testing (as part of TTTC TTEP) in the past; e.g., ITC and DATE. In addition, Hamdioui has been giving tutorials/consultancy on memory testing and reliability for worldwide leading semiconductor companies in Europe, USA and Asia.

 Session Abstract:  Compute-In Memory (CIM) or In-Memory Computing (ICM) is receiving a lot of attention and traction in recent years for many application including Artificial Intelligence (AI) Deep Learning (DL) ones. CIM combines the power of large data storage and concurrent computation in one module thus achieving significant reduction computation energy.  Memories used to realize CIM allows not only for data-storage, but also for the execution of logical and arithmetic operations.

Different memory architectures and technologies are being investigated for CIM, including CMOS traditional ones such as SRAM as well as emerging non-volatile ones such as RRAMs.  Combining the data-storage memory capability with logic and arithmetic operations introduces significant testing challenges. New fault models and test approaches are needed to enable the use the CIM in silicon products.

The sessions first introduce CIM concept including its the potential applications and different implementation flavors. Then the session covers the testing of SRAM based and RRAM based CIM.

Session format:  The session will be 90 minutes and will have three talks addressing In Memory computing architectures and testing.

talks and speakers

Talk 1: In-Memory Computing: History, Overview, Current and Future Directions

Speaker: Professor Narish Shanhbag

Abstract:  In-memory computing (IMC) has become an active area of research in the circuits community.

IMC addresses the energy and latency costs of memory accesses that dominate when processing AI workloads. It does so by transforming the conventional memory read access into one that computes AI functions of data by employing analog computations. As a result, IMC chips have demonstrated > 100X reduction in the energy-delay product over equivalent von Neumann architectures at ISO-accuracy. However, today, bank-level IMC designs have matured and efficiency gains have stagnated. This talk will provide a historical overview of the technology, describe current trends, and identify future opportunities and challenges in deploying IMCs in emerging applications.

Short bio:

Naresh R. Shanbhag is the Jack Kilby Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign.

He received his Ph.D. degree from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories at Murray Hill where he led the design of high-speed transceiver chipsets for very high-speed digital subscriber line (VDSL), before joining the University of Illinois at Urbana- Champaign in August 1995. He has held visiting faculty appointments at the National Taiwan University (Aug.-Dec. 2007) and Stanford University (Aug.-Dec. 2014). His research focuses on the design of energy-efficient systems for machine learning, communications, and signal processing spanning algorithms, architectures, and integrated circuits. He has more than 200 publications in this area and holds thirteen US patents.Dr. Shanbhag received the 2018 SIA/SRC University Researcher Award, became an IEEE Fellow in 2006, received the 2010 Richard Newton GSRC Industrial Impact Award, the IEEE Circuits and Systems Society Distinguished Lectureship in 1997, the National Science Foundation CAREER Award in 1996, and multiple best paper awards. In 2000, Dr. Shanbhag co-founded and served as the Chief Technology Officer of the Inter-symbol Communications, Inc., which introduced mixed-signal ICs for electronic dispersion compensation of OC-192 optical links, and became a part of Finisar Corporation in 2007. From 2013-17, he was the founding Director of the Systems On Nanoscale Information fabriCs (SONIC) Center, a 5-year multi- university center funded by DARPA and SRC under the STARnet program.

Talk 2: Testing Computation-in-Memory Architectures Based on Memristive Devices

Speaker: Said Hamdioui, Delft University of Technology, The Netherlands


Testing of RRAM based CIM devices is fundamentally different from testing traditional memories. Non-volatile memories used to realize CIM concepts allows not only for data-storage (i.e., memory configuration), but also for the execution of logical and arithmetic operations (i.e., computing configuration). Therefore, not only significant design changes are needed in memory array and/or in the peripheral circuits, but also new fault models and test approaches are needed. Moreover, RRAM based CIM makes use of non-linear non-volatile devices making the defect modeling with traditional linear resistor inappropriate for such device defects. Hence, even the way of doing defect modeling has to change. This talk discusses testing for RRAM based CIM and highlights the test challenges and how testing CIM dies is different from the traditional way of testing logic and memory. Methods for defect modeling, fault modeling, and test development will be discussed. The talk demonstrates that unique faults can occur in the CIM die while in the computation configuration, and that these faults cannot be detected by just testing the CIM die in the memory configuration. Moreover, it shows that testing the CIM die in the computation configuration reduces the overall test time while improving the outgoing product quality.

Talk 3: Fully Digital Compute In Memory Design and Test challenges

 Speaker: Saman Adham, TSMC, North America, USA,


Computing-in-memory (CIM) is being widely explored to minimize power consumption in data movement and multiply-and-accumulate (MAC) for edge-AI devices. Although most prior work focuses on analog-based CIM (ACIM) to leverage the BL charge/discharge operation, the lack of accuracy caused by transistor variation and the ADC is a concern. In contrast, a digital-based CIM (DCIM) approach realizes enough accuracy and flexibility for various input and weight bit widths while also benefiting from technology scaling. This presentation provides an overview of SRAM based DCIM macro using 1R1W bit-cell and cascaded adders. The DCIM macro can realize simultaneous MAC + write operations and wide range dynamic voltage-frequency. A programmable BIST based test solution is designed and implemented for the DCIM macro. Special features were designed in the BIST engine to enable DCIM macro performance and power characterization. Fault simulation shows the BIST achieved > 99% test coverage. The BIST test results were validate on a test chip.

Intended audiences

This session will be interesting for a wide range of audiences including:

  • VLSI designers; learn what compute in memory is all about and understand different implementation architecture
  • Test engineers; learn the complexity of CIM design and how test should be designed to achieve high quality products
  • Researchers; interested in exploring new CIM architectures and implementations

Hardware Security Certification

Session format:  The session will be 90 minutes and will have three talks

talks and speakers

Talk 1: Latest Cybersecurity regulations, certifications and labeling trends

Speaker: Rachel Menda-Shabat, Winbond, Israel,

Abstract: The session will present the latest trends in regulations and certifications related to Cyber security in region and industrial aspects:  In the region diminution – EU Cybersecurity Act and US IoT Cybersecurity Improvement Act while presenting latest actions which were taken.  At the industrial dimension – Radio Equipment Directive (RED) Delegated Act latest security requirements, IoT consumer, ETSI EN 303 645, industrial requirements, IEC 62443, and the Automotive latest cybersecurity regulations, ISO21434 and WP.29 UN-155.

The session will present the actual and the planned labeling for cybersecurity certified products as implemented in Finland and Singapore and planned to be adopted in Europe.

Short bio:

Mrs. Rachel Menda-Shabat has over 20 years of experience in security product development and certification.

She is the Director of Certification at Winbond, managing the security certification of Winbond products. Led a number of certifications such as Common Criteria, FIPS 140-2, SESIP, PSA, EMVco and more.

She is the Chairwoman of Eurosmart ITSC’s 3S in SoC PP Working Group, and Co-Chair of Eurosmart IoT task force and Remote working at ISCI-WG1.

Last year she was rewarded for GlobalPlatform Star Reward for her contribution to SESIP, in particular in driving SESIP to NIST database as a methodology relevant for the compliance demonstration of IoT products to the NIST 8259A requirements.

She is Involved in worldwide security groups, such as CCUF, GlobalPlatform and ISO.

Rachel has a Masters degree in Business Administration.
Hardware Security Certification

Talk 2: GlobalPlatform: 20 years of Security evaluation on secure components

Speaker:  Gil Bernabeu, Technical Director, GlobalPlatform

Abstract: This presentation will share the experience of GlobalPlatform in the last 20 years about the security evaluation of secure component. Secure component is a combination of hardware and software to create an isolated environment to protect application and data. There are multiple types of secure components based on different chips and SOC designs. GlobalPlatform is working to clarify level of security provided by these different solutions. Also an important effort is about improving evaluation methodologies , reusability of results and time to market of certified product

Short bio:

Mr Bernabeu is Head of R&D and Innovation funding at Thales DIS. In this role he facilitates open collaborations on innovative funded project to accelerate Thales DIS road map and services.

Mr Bernabeu was elected as GlobalPlatform’s Technical Director in 2005. His main role is to drive forward the development of GlobalPlatform’s specifications to deploy secure services. Mr Bernabeu also acts as GlobalPlatform’s central technical liaison point, coordinating the efforts of the organization’s three technical committees – Secure Element (SE), Trusted Execution Environment (TEE) and Trusted Platform Services (TPS) – and the GlobalPlatform Task Forces with external partners.

Talk 3: Hardware Security in IoT Platforms and Certification

Speaker:  Tung-Yi Chan, Vice Chairman & Deputy CEO, Winbond

Abstract: Due to limited OS/firmware capability and insufficient external support in IoT devices, there are increasing concerns on the security of IoT devices. Like the carbon net zero mandated by governments and committed by corporates, security regulations on internet connected devices are to be implemented and enforced in coming years. Security certifications are required by governmental and industrial regulations to validate the security of IoT products in the market.
This speech demonstrates how to integrate secure MCU, secure memory and firmware to build secured IoT platforms with “Root of Trust” and “cyber resilience”. The security certification ecosystem and certification process flow are illustrated with the certification of secure Flash memory.

Short bio: Tung-Yi has been the president of Winbond Electronics Corp. in 2009 – 2020, a world leading code storage Flash supplier and one of the major suppliers in specialty DRAM.

He has worked in Intel in advanced MOSFET device technology, Cypress in SRAM and EPROM technologies, and Siliconix in power device technologies. He has been CEO of BCD Semiconductor in Shanghai China, an IDM in power devices. He is currently vice chairman and deputy CEO of Winbond Electronics Corp.
Through work in those companies and different geographic area, Tung-Yi accumulated wide experience in technology development, marketing, sales, and business management.He received BS degree in Electrical Engineering from National Taiwan University, MS and Ph.D. degrees in Electrical Engineering from the University of California, Berkeley, and MS degree in Management from Stanford University

Intended audiences
This session will be interesting for a wide range of audiences including: (select or modify what’s appropriate)
 VLSI designers; e.g., learn what key aspects to consider when …
 Computer architecture engineers; e.g., exploring the use of …
 Test engineers; learn how new test methods …
 Device researchers; learn about the … device technology and its challenges
 Researchers interested in …

Tutorial on Quantum Circuit Testing (from test engineers’ perspective)


  • James Chien-Mo Li, National Taiwan University, Taiwan,

Short bio:

James Chien-Mo Li received his BSEE in 1993 from National Taiwan University, Taiwan.

He received his MSEE and PhD in electrical engineering from Stanford University in 1997 and 2002 respectively.  He is currently a professor of Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan.  His research interest includes quantum circuit testing, ATPG, machine learning for test applications, low power testing, and diagnosis.  He has coauthored three books in EDA and testing.

 Abstract:  Quantum circuits (QC) are becoming an important computational technology in many useful applications, such as machine learning, optimization, and cryptography.  Testing QC, however, is completely different from testing classical circuits.  In this tutorial, we will introduce basic concepts about QC from test engineers’ perspective.  Then, we will introduce error, noise, and fault models for quantum circuits.  Finally, we will propose new test generation and diagnose techniques for quantum circuits.

 Session format

The session will be 90 minutes and will have three parts addressing three topics.

Overview of talks and speakers

The session will consist of the following three talks:

Part 1: Basic Concepts about Quantum Circuits

Abstract:  In this part, we will introduce basic concepts about quantum circuits.  We will use simple mathematical formula to describe the behavior of quantum circuits.  We will also explain some famous quantum algorithms from circuit designer’s perspective.

Part 2: Errors, Noise, and Faults

Abstract:  In reality, noisy intermediate scale quantum (NISQ) circuits are vulnerable to errors.  Error sources include environmental disturbance qubit de-coherence, control imperfection, and so on manufacturing defects.  Errors sources can be divided into noise and faults.  We will introduce how to model and mitigate noise and faults in quantum circuits.

Part 3: Test and Diagnosis of Quantum Circuits

Abstract:  As quantum circuits keep scaling, it is very needed to test and diagnose quantum circuits.  However, traditional methods are no longer suitable for quantum circuits.  In this part, we will introduce new automatic test generation (ATG) from test designer’s perspective.  We will also propose new diagnosis techniques for quantum circuits.


Intended audiences

This session will be interesting for audiences … : (select what’s appropriate)

  • VLSI designers interested in quantum computing
  • Test engineers interested in quantum computing
  • Researchers interested in quantum computing

Design and Test of Wide-Bandgap Power Devices and Circuits

 Session format:  The session will be 90 minutes and will have three talks addressing the device characterization, power system design, and defect analysis of wide-bandgap semiconductor devices.

 Abstract:  Abstract: High-power devices using wide-bandgap compound semiconductors such as GaN and SiC are getting more and more popular in various applications from 5G and electric vehicles to renewable energy, thanks to their ability to support faster-switching speed and higher-voltage operation while achieving higher power efficiency and better heat conduction. In this special session, three talks are invited to give a practical overview. The issues covered include device characterization, high-power subsystem design, measurement, and testing strategies.


  • Shi-Yu Huang, National Tsing Hua University, Taiwan (

Shi-Yu Huang received his Ph.D. degree in Electrical and Computer Engineering from the University of California, Santa Barbara, in 1997.

Since 1999, he has joined National Tsing Hua University, Taiwan until now. His recent research is concentrated on all-digital timing circuit designs, such as all-digital phase-locked loop (PLL), an all-digital delay-locked loop (DLL), and time-to-digital converter (TDC), and their applications to parametric fault testing and reliability enhancement for 3D-ICs. Recently, he is also involved in the design and test of GaN/SiC power circuits and systems. He has published more than 160 technical papers (including 46 IEEE journal papers). Dr. Huang ever co-founded a company in 2007-2012, TinnoTek Inc., specializing in a cell-based PLL compiler and system-level power estimation tools. Prof. Huang is a senior member of IEEE.

talks and speakers

Talk 1: The Importance and Demand Market of SiC Substrate Defect Testing

Abstract:  SiC is a potential material for high-power devices such as EVs and green energy applications. If it’s used as a substrate for GaN epitaxial layer, it’s also highly recommended to make a 5G or 6G communication device. The above application makes SiC device has more than a 20% CAGR growth rate before 2027. However, growing SiC substrate is more difficult than Si substrate. The main reason is that SiC has silicon and carbide two elements, during the high-temperature crystallization process, it might generate lots of defects. Some of the key defects might deliver to the epitaxial layer and device, and finally, make the device fail. In this talk, we will introduce the importance and market of SiC substrate defect testing.

Short bio:

  • Wen-Chi Chang, Industrial Technology Research Institute, Taiwan (
Wen-Chi Chang received her Ph.D. degree in the Institute of Applied Mechanics from National Taiwan University, in 2015. Since 2015, she has joined TSMC as an R&D process engineer in the epitaxy department. In 2020, she joined Industry, Science, and Technology International Strategy Center in ITRI doing marketing research. Her main research subject is semiconductor equipment marketing trend analysis. Recently, she also joined ITRI SiC strain/stress metrology team, keeps closely watching the compound semiconductor inspection technology and the future demand market.

Intended audiences

This session will be interesting for a wide range of audiences including: (select what’s appropriate)

  • Wide-bandgap power device engineers.
  • Wide-bandgap power circuits/systems designer.
  • Test engineers and researchers who want to expand their scopes of interest to Wide-bandgap power devices/circuits/systems.

Talk 2: Validation of SPICE models for commercial SiC MOSFETs

Speaker: Hung-Yi Teng, Industrial Technology Research Institute (ITRI)

Abstract:  Silicon carbide (SiC) MOSFETs are promising for electric vehicles because they show excellent performance in low on-resistance, high-frequency, and high-speed switching, as well as in operation at high temperatures. The accuracy of the SPICE model of SiC MOSFET is crucial when evaluating the performance of power devices. We validated the SPICE model of commercial 1.2kV SiC MOSFETs regarding its static characteristics, dynamic characteristics, and switching characteristics. In this paper, we will introduce our validation methodology and present major findings observed from the validation results. Furthermore, how to improve the accuracy of the SPICE model of SiC MOSFETs will also be discussed.

Short bio:   Hung-Yi Teng received his Ph.D. degree in Computer Science and Information Engineering from National Chung Cheng University, Chiayi, Taiwan, in 2013. He is currently working as a software/firmware engineer in ITRI Southern Region Campus. Also, he is recently involved in GaN/SiC power device and system development. His research interests focus on model validation of SiC MOSFET and GaN-based motor drive.

 Talk 3: Practice Design Experiences on a Multi-Voltage-Level Motor Driver System using a Power Inverter

Speaker: Chih-Chung Chiu, Industrial Technology Research Institute (ITRI), Taiwan

Abstract:   In this talk, we share our design experiences on a motor driver system incorporating power inverters. To support the switching among several different operating voltages, the controller of the power inverters based on pulse-width modulation have to be tailored in a way to mix the currents from different power conversion paths, so that the performance is optimized with robust operation at the same time. Simulation results and the measurement results of a prototype system are presented to demonstrate how the adopted pulse-modulation schemes for the power inverters, including CPS-SPWM and PD-SPWM schemes can improve the system’s stability.

Short bio:  Chih-Chung Chiu received the MS from the Department of Electronics Engineering, Yuan Ze University. After working at Foxconn and Delta from 2010 to 2015, he joined Powertrain Controller as an R&D in Electronics Engineering. In 2016, he transferred to ITRI, where he is now a Deputy Technical Manager in the ITRI of Electrical Engineering. His research focuses on embedded systems, machine vision, and power electronics signal processing.

Papers from ITC Asia

A Decision Tree-Based Screening Method for Improving Test Quality of Memory Chips

Authors:  Ya-Chi Cheng, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang and Gordon Liao

Abstract:  There is a growing demand for high-reliability and high-quality integrated circuit (IC) products, while their test costs should be kept as low as possible. We investigate the test process of advanced memory chips, where the high temperature operating life (HTOL) test has been used to determine their intrinsic reliability. This high temperature sampling test can run from 168 to 1,000 hours, so it is time-consuming and expensive. Recently, machine learning (ML) algorithms have been used to solve classification problems, so far as good training data can be obtained. In our case, there is already a large amount of parametric test data generated from the existing test flow. Therefore, in this work, we propose a decision tree (DT)-based screening method to predict weak (unreliable) dies that would fail the HTOL test. We show that experienced test engineers can prioritize the parametric test data for better use of the DT model. Finally, we take advantage of the high interpretability of DT to develop the multi-feature heuristics, which can be used to improve the quality of final test (FT). Keeping the overkill rate at 0%, our heuristics can screen out 25% more bad dies, i.e., we can improve the FT quality without additional cost.

 Fault Resilience Techniques for Flash Memory of DNN Accelerators

Authors:  Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong and Kohei Miyase

 Abstract:  Deep neural networks (DNNs) are being widely used in smart appliances, face recognition and autonomous driving. The trained weight data are usually stored in flash memory which suffers from reliability and endurance issues. Owing to the inherent error tolerability for DNN applications, address remapping techniques are proposed for protecting weight data stored in flash memory. Bit significances are first analyzed and then a weight transposer is proposed for remapping significant weight bits to fault-free or much reliable flash cells. A bipartite graph model is developed for modeling address remapping. The corresponding hardware architectures for address remapping are also proposed. We use the deep learning framework pytorch for evaluating inference accuracy for different DNN models. Experimental results show that based on 0.01 % injected BER in the weight data, the accuracy losses of widely used DNN models are less than 1 % with negligible hardware overhead.