In-Memory Computing Design and Test challenges

Organizer(s):

• Saman Adham, TSMC, North America, USA, samana@tsmc.com

Saman Adham is a Senior Manager at TSMC North America, in Austin Texas.

He received a BS and MS in Electrical Engineering from the University of Baghdad, Iraq, in 1977 and 1979 respectively and his PhD from Queens University, Canada in 1991. Dr. Adham has over 32 years of industrial experience with a proven track record in the area of design for test (DFT) and built-in self-test. He joined Nortel Networks in 1991 and then became the DFT advisor of Nortel Networks, developing design for test methodologies and built-in self-test. From 1999 to 2009, Dr. Adham was the Director of Engineering at LogicVision Inc. He joined TSMC Ottawa, Canada in 2009 as Senior Manager, BIST and ASIC design group and recently moved to TSMC North America in Austin, Texas.  Dr. Adham has a considerable publication record in the area of design for test and built-in self-test. He also holds more than 50 US patents and several pending patents. He is the chair of IEEE Std 1450.6.2 working group, standardizing memory test modeling. Additionally, he is a reviewer for many DFT/BIST, hardware security journals and conferences.

• Second organizer: Said Hamdioui, Delft University, S.Hamdioui@tudelft.nl

Said Hamdioui is Professor on Dependable and Emerging Computer Technologies and Head of the Computer Engineering Laboratory at Delft University of Technology (TUDelft).

Prior to joining TUDelft, he worked for Intel, Philips Semiconductors and NXP Semiconductors. His research focuses on two domains: Dependable CMOS nano-computing (including Reliability, Testability, Hardware Security) and emerging technologies and computing paradigms.Hamdioui owns two patents, has published/contributed to three books, and has authored over 250 publications in major journals and conference proceedings. He was/is on the editor board of many journals (TVLSI, JETTA, D&T, JETC, etc), and has received many best paper awards/nominations at leading conference (ITC, ETS, DATE, ICCD, ISVLIS, etc.). Hamdioui has presented many tutorials about memory testing (as part of TTTC TTEP) in the past; e.g., ITC and DATE. In addition, Hamdioui has been giving tutorials/consultancy on memory testing and reliability for worldwide leading semiconductor companies in Europe, USA and Asia.

 Session Abstract:  Compute-In Memory (CIM) or In-Memory Computing (ICM) is receiving a lot of attention and traction in recent years for many application including Artificial Intelligence (AI) Deep Learning (DL) ones. CIM combines the power of large data storage and concurrent computation in one module thus achieving significant reduction computation energy.  Memories used to realize CIM allows not only for data-storage, but also for the execution of logical and arithmetic operations.

Different memory architectures and technologies are being investigated for CIM, including CMOS traditional ones such as SRAM as well as emerging non-volatile ones such as RRAMs.  Combining the data-storage memory capability with logic and arithmetic operations introduces significant testing challenges. New fault models and test approaches are needed to enable the use the CIM in silicon products.

The sessions first introduce CIM concept including its the potential applications and different implementation flavors. Then the session covers the testing of SRAM based and RRAM based CIM.

Session format:  The session will be 90 minutes and will have three talks addressing In Memory computing architectures and testing.

talks and speakers

Talk 1: In-Memory Computing: History, Overview, Current and Future Directions

Speaker: Professor Narish Shanhbag

Abstract:  In-memory computing (IMC) has become an active area of research in the circuits community.

IMC addresses the energy and latency costs of memory accesses that dominate when processing AI workloads. It does so by transforming the conventional memory read access into one that computes AI functions of data by employing analog computations. As a result, IMC chips have demonstrated > 100X reduction in the energy-delay product over equivalent von Neumann architectures at ISO-accuracy. However, today, bank-level IMC designs have matured and efficiency gains have stagnated. This talk will provide a historical overview of the technology, describe current trends, and identify future opportunities and challenges in deploying IMCs in emerging applications.

Short bio:

Naresh R. Shanbhag is the Jack Kilby Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign.

He received his Ph.D. degree from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories at Murray Hill where he led the design of high-speed transceiver chipsets for very high-speed digital subscriber line (VDSL), before joining the University of Illinois at Urbana- Champaign in August 1995. He has held visiting faculty appointments at the National Taiwan University (Aug.-Dec. 2007) and Stanford University (Aug.-Dec. 2014). His research focuses on the design of energy-efficient systems for machine learning, communications, and signal processing spanning algorithms, architectures, and integrated circuits. He has more than 200 publications in this area and holds thirteen US patents.Dr. Shanbhag received the 2018 SIA/SRC University Researcher Award, became an IEEE Fellow in 2006, received the 2010 Richard Newton GSRC Industrial Impact Award, the IEEE Circuits and Systems Society Distinguished Lectureship in 1997, the National Science Foundation CAREER Award in 1996, and multiple best paper awards. In 2000, Dr. Shanbhag co-founded and served as the Chief Technology Officer of the Inter-symbol Communications, Inc., which introduced mixed-signal ICs for electronic dispersion compensation of OC-192 optical links, and became a part of Finisar Corporation in 2007. From 2013-17, he was the founding Director of the Systems On Nanoscale Information fabriCs (SONIC) Center, a 5-year multi- university center funded by DARPA and SRC under the STARnet program.

Talk 2: Testing Computation-in-Memory Architectures Based on Memristive Devices

Speaker: Said Hamdioui, Delft University of Technology, The Netherlands

Abstract:

Testing of RRAM based CIM devices is fundamentally different from testing traditional memories. Non-volatile memories used to realize CIM concepts allows not only for data-storage (i.e., memory configuration), but also for the execution of logical and arithmetic operations (i.e., computing configuration). Therefore, not only significant design changes are needed in memory array and/or in the peripheral circuits, but also new fault models and test approaches are needed. Moreover, RRAM based CIM makes use of non-linear non-volatile devices making the defect modeling with traditional linear resistor inappropriate for such device defects. Hence, even the way of doing defect modeling has to change. This talk discusses testing for RRAM based CIM and highlights the test challenges and how testing CIM dies is different from the traditional way of testing logic and memory. Methods for defect modeling, fault modeling, and test development will be discussed. The talk demonstrates that unique faults can occur in the CIM die while in the computation configuration, and that these faults cannot be detected by just testing the CIM die in the memory configuration. Moreover, it shows that testing the CIM die in the computation configuration reduces the overall test time while improving the outgoing product quality.

Talk 3: Fully Digital Compute In Memory Design and Test challenges

 Speaker: Saman Adham, TSMC, North America, USA, samana@tsmc.com

Abstract:

Computing-in-memory (CIM) is being widely explored to minimize power consumption in data movement and multiply-and-accumulate (MAC) for edge-AI devices. Although most prior work focuses on analog-based CIM (ACIM) to leverage the BL charge/discharge operation, the lack of accuracy caused by transistor variation and the ADC is a concern. In contrast, a digital-based CIM (DCIM) approach realizes enough accuracy and flexibility for various input and weight bit widths while also benefiting from technology scaling. This presentation provides an overview of SRAM based DCIM macro using 1R1W bit-cell and cascaded adders. The DCIM macro can realize simultaneous MAC + write operations and wide range dynamic voltage-frequency. A programmable BIST based test solution is designed and implemented for the DCIM macro. Special features were designed in the BIST engine to enable DCIM macro performance and power characterization. Fault simulation shows the BIST achieved > 99% test coverage. The BIST test results were validate on a test chip.

Intended audiences

This session will be interesting for a wide range of audiences including:

• VLSI designers; learn what compute in memory is all about and understand different implementation architecture
• Test engineers; learn the complexity of CIM design and how test should be designed to achieve high quality products
• Researchers; interested in exploring new CIM architectures and implementations