We have a set of 31 interesting and diverse posters for you this year. Posters present a nice information opportunity to discuss various works with the authors.
The poster session will be in the exhibit area on Wednesday from 12:00 – 2:00 PM.
Poster Listings
[154] Patrick Chen (Intel Corporation, Taipei Taiwan) and James Grealish (Intel Corporation, Hillsboro OR U.S.A). IEEE 1149.1-2013 Intel Product Compliance and Industry Enablement Plans.
Abstract. This poster is to update current Intel product 1149.1-2013 compliance status and plans to enable industry including vendors and customers
[155] Michele Portolan (TIMA), Riccardo Cantoro (Politecnico di Torino), Ernest Sanchez (Politecnico di Torino) and Matteo Sonza Reorda (Politecnico di Torino). A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks .
Abstract. IEEE 1687 introduces several novelties, like Reconfigurable Scan Networks, which offer important advantages but can result in extremely complex integrity tests. In this poster we present an innovative functional approach.
[156] Thomas Klotz (Hochschule Rosenheim) and Martin Versen (Hochschule Rosenheim). Interpreter of MATLAB/Simulink MAT-Output Files for use as Test and Verification Stimulus for Verilog Simulations with Cadence NCSim.
Abstract. A test circuit is implemented in Verilog with MathWorks’ HDL Coder. An interpreter converts the signal states to a Verilog stimulus. After Cadence import, the design is simulated with NCSim.
[157] Kalpana Senthamarai Kannan (Grenoble-INP/TIMA), Michele Portolan (Grenoble-INP/TIMA) and Lorena Anghel (Grenoble-INP/TIMA). Run-Time Aging Prediction Through Machine-Learning .
Abstract. Recent technologies are extremely sensitive to aging, and a-priori margin estimation is difficult and imprecise. The method we propose allies embedded monitors and machine learning to predict aging during runtime.
[158] Ernst Wahl (HiTestWare LLC). New Standard Test Interface Language (STIL) Applications.
Abstract. Publication of Standard Test Interface Language (STIL) for Test Flow Specification (IEEE Std. 1450.4-2017) facilitates new applications for the STIL family of standards such as tester-independent IC test program specification.
[159] George Lawton Iii (Lawton software llc). Dynamic Cloud-Based Data Collection System.
Abstract. A schema-less cloud-based distributed data collection system with dynamic validation and comprehensive system status and alerting provided a reconfigurable data collection system to solve evolving incoming data schemas.
[160] Darshal Patel (AMD) and Khushboo Agarwal (AMD). Layout aware wrapper for IP cores.
Abstract. SOCs are built up of multiple embedded cores with test wrapper around them. This poster describes methodology to use physical location and functional testcase requirements to build wrapper chains.
[161] Jeff Rearick (AMD), Al Crouch (Amida), Martin Keim (Mentor, A Siemens Business), Michael Laisne (Dialog Semi) and Glenn Colon-Benet (Intel). IEEE P1687.1: Extending 1687 to non-TAP Interfaces.
Abstract. This poster describes the work of the IEEEP1687.1 Working Group toward developing a standard for accessing on-chip instruments through a 1687 network connected an interface other than the IEEE1149.1 TAP.
[162] Anthony Coyette (ON Semiconductor), Ronny Vanhooren (ON Semiconductor), Wim Dobbelaere (ON Semiconductor), Baris Esen (Katholieke Universiteit Leuven), Nektar Xama (Katholieke Universiteit Leuven), Jhon Caicedo (Katholieke Universiteit Leuven) and Georges Gielen (Katholieke Universiteit Leuven). Visually-enhanced Dynamic Part Average Testing.
Abstract. In this work, a method is presented which combines the data from the visual inspection of wafers and the Dynamic Part Average Testing algorithm applied to the specifications.
[163] Jungho Kang (Samsung Electro-Mechanics) and Kyungsoo Chae (Samsung Electro-Mechanics). Non-Contact Probing for Electrical Connectivity of Printed Circuits.
Abstract. This study proposes a new non-contact test solution for printed circuit boards. The experiment shows that common circuit pattern defects such as open, short, and via open can be detected.
[164] Jim Johnson (SiliconAid Solutions), Alfred Crouch (Amida) and Bill Atwell (SiliconAid Solutions). IJTAG Security.
Abstract. This poster will show several security vulnerabilities and possible ways to mitigate these issues within an IJTAG network. Different levels of security will be shown meet specific device requirements.
[165] Jim Johnson (SiliconAid Solutions), Alfred Crouch (Amida) and Bill Atwell (SiliconAid Solutions). IEEE 1687 (IJTAG) Evolution.
Abstract. Poster shows the evolution of IJTAG. How IJTAG fits with other major standards for a total solution. The addition of IEEE 1687.1 and 1687.2 will enhance the solution even more.
[166] Rene Krenz-Baath (HSHL). Concurrent IJTAG.
Abstract. In this work we are proposing a novel partitioning concept to a reconfigurable test infrastructure in order to enable an independent operation of different sections of the test infrastructure.
[167] Jeffrey Hung (Microsoft) and Vidya Neerkundar (Mentor, A Siemens Business). Are You Really Testing Your Memory? Automating Test and Verification of All Memory Functionality.
Abstract. The MBIST flow is augmented by leveraging advanced tool features to automate test and verification of both the memory core and peripheral timing/power controls typically ignored by traditional models.
[168] Jeff Rearick (AMD), Steve Sunter (Mentor, A Siemens Business) and Vladimir Zivkovic (Cadence). IEEE P1687.2: Extending 1687 to Analog Circuits.
Abstract. This poster describes the status and plans of the IEEE P1687.2 Working Group toward its goal of enabling analog tests to be retargeted via IEEE1687 mechanisms.
[169] Karthik Subramanian (Ambarella), Praveen Jaini (Ambarella), Adrian Arozqueta (Mentor, A Siemens Business) and Mohammed Abdelwahid (Mentor, A Siemens Business). In-system and Manufacturing Test Flow for Large Automotive ICs .
Abstract. a DFT architecture and supporting flow addressing the challenges for large automotive chip is proposed based on an industrial flow example including challenges and trade-off to reduce design cycle cost.
[170] Xijiang Lin (Mentor, A Siemens Business) and Sudhakar Reddy (University of Iowa). On Generating Fault Diagnosis Patterns in the Presence of Xs.
Abstract. For logic diagnosis, we show that earlier methods may generate invalid tests to distinguish pairs of faults in the presence of unknowns. A method to generate valid tests is proposed.
[171] Vidya Achari (Texas Instruments Inc.) and Saminah Chaudhry (Texas Instruments Inc.). Enabling High Quality Silicon with Collaboration of Post Silicon Validation and Systems.
Abstract. Poster on Validating device smartly while improving quality by collaborating with system engineers to define the system-level tests, push validation beyond the limits, define spec compliance and automate datasheet generation.
[172] Stacy Ajouri (Texas Instruments) and Dennis Foreman (Texas Instruments). Tester Board tracking system using Streaming RITdb.
Abstract. This poster will present an application using IOT methodology to track and analyze the movement of tester boards as well as provide real time feedback to the test operation.
[173] Jon Ferguson (Graphcore), Paul Freeman (Graphcore), Paul Hudson (Mentor, A Siemens Business) and Lee Harrison (Mentor, A Siemens Business). ATE Not Required: A Complete Test Solution to Accelerate First Silicon Shipping of a Large AI Design.
Abstract. We demonstrate a fully automated test execution solution that is centered on SiliconInsight. We brought up all DFT patterns very fast, and were shipping first die samples ahead of schedule.
[174] Vidya Neerkundar (Mentor, A Siemens Business) and Ron Press (Mentor, A Siemens Business). Effective Testing of Identical Hierarchical Cores.
Abstract. This poster explains upfront design planning, combined with optimized compression architecture within the hierarchical core(s) that helps benefit from better resource utilization at the chip-level.
[175] Tal Kogan (Intel) and Amihay Rabenu (Inetl). Optimal SCAN Vector Count.
Abstract. A novel approach for finding the optimal SCAN configuration is introduced, minimizing the vector count at SoC level. This will lead to minimized overall Test time and Memory footprint.
[176] Anne Meixner (The Engineers’ Daughter LLC), Salem Abdennadher (Intel), Stepen Sunter (Mentor, A Siemens Company) and Peter Sarson (Dialog Semiconductor). What’s up with Analog Test Coverage?: IEEE P2427 IEEE Working Group Progress.
Abstract. Draft standard has been produced that includes: state-of-the-art in analog fault simulation summary, an extensive set of concise definitions, and rules for clear reporting on analog defect and fault coverage.
[177] Marvin Yang (Advantest), Alex Fan (Advantest Inc.) and Ashley Huang (Advantest Inc.). An improvement of routability of memory test interface board by auto pin assignment algorithm.
Abstract. This paper is to introduce an auto pin assignment algorithm to improve the routability of memory test interface board design.
[178] Juan Pulido Sanchez (ON Semiconductor) and Rahul Singhal (Mentor, A Siemens Business). TAP based Scan Testing of High Performance Image Sensor Chip.
Abstract. The poster show an implementation of TAP based scan-testing implementation to standardize DFT pin methodology for On-Semiconductor’s chip. Test coverage of 98.9% stuck-at and 87% at-speed testing was achieved.
[179] Hans Martin von Staudt (Dialog Semiconductor). Error Sources to Trim Distributions.
Abstract. This poster approaches the mathematical description of process variation to the trim distributions. The use of self-trim techniques shapes the resulting trimmed distributions significantly but it doesn’t change the width.
[180] Kevin Fan (Advantest Taiwan Inc). Discrete-Time Controller Implementation for Automotive High Reliability Testing.
Abstract. This paper specific challenges related to automotive device high reliability requirement,performance evaluation by FVI16 with Digital Feedback Loop capability to assure quality of test and achieve 13% test time improvement.
[181] Jackie Cooper (Intel). Method to Measure and Improve Toggle Coverage During High Volume Quick Kill Stress.
Abstract. This poster presents a method to calculate toggle coverage using customization options in Mentor’s commercial ATPG solution and shows how coverage can be improved during stress 10-15%.
[182] Rahul Singhal (Mentor, A Siemens Business), Imtiaz Ahmed (Qualcomm Technologies, Inc.) and Subhash Baraiya (Qualcomm India Private Limited). Low Pin Count Testing of an Industry Transceiver Chip.
Abstract. This solution shows low pin count testing implementation of an Industry transceiver chip using Embedded Deterministic Test (EDT)
[183] Vidya Achari (Texas Instruments Inc.), Sandeep Achari (Soliton technologies Inc) and Vishnuprasad Narayanan Kutty (soliton technologies inc). Influence of Machine Learning on Post Silicon Validation & Analysis.
Abstract. This poster discusses use of Machine Learning techniques to reduce the engineering effort in analyzing data and Test-time reduction by highlighting the potential risks earlier, derived from previous device data.
[184] Hyung Soon Kim (Samsung Electronics), Shin Ho Kang (Samsung Electronics) and Gyu Yeol Kim (Samsung Electronics). Efficient Rising Time Measurement through a Level TPD technique by using TDR Function of Automatic Test Equipment.
Abstract. This paper suggests a new measurement technique dubbed as Level TPD which efficiently measures the rising time of transmission lines, employing Time Domain Reflectometry of Automatic Test Equipment.
[185] Michael Laisne (Dialog Semiconductor), Luiz Razera (Dialog Semiconductor), Hans Martin von Staudt (Dialog Semiconductor), Bindhu Vasu (Dialog Semiconductor) and Doru Cioaca (Dialog Semiconductor). Novel IJTAG and IJTAG.1 Architecture Alternatives.
Abstract. This poster presents some novel approaches to IJTAG and IJTAG.1 architectures including an instrument interface capable of controlling the scan chains depending on the instrument state and other unique features.
ITC Asia Summary
/0 Comments/in Headlines /by Ron PressITC-Asia 2018
This year ITC-Asia has more than 450 recorded attendees, which include both ITC-Asia’18 registrants (120+) and CTC’18 registrants (330+).
The opening ceremony of ITC-Asia 2018 was held in the morning of August 16. Prof. Kwang-Ting (Tim) Cheng, the General Co-Chair, gave the ITC-Asia 2018 opening message. Prof. Xiaowei Li (from CAS) gave the welcome message from the ITC-Asia 2018 General Co-Chair. Prof. Huawei Li (from Institute of Computing Technology, Chinese Academy of Sciences), the ITC-Asia 2018 Program Co-Chair, introduced the ITC-Asia 2018 technical program and social event as well.
Congratulations to Prof. Min!
Parts of the ITC-Asia’18 attendees took a group photo during the coffee break on August 16 morning.
The ITC-Asia’18 program includes Tutorial Courses, Keynote Speeches, Panel discussion, Paper sessions, Special Sessions, Industrial Sessions, Exhibition, Social Event, and Banquet.
After the opening ceremony, the ITC-Asia 2018 Program Co-Chair, Prof. Xiaoqing Wen (from KIT), moderated the three keynote speeches, given by Dr. Janusz Rajski (from Mentor, A Siemens Business), Prof. Li-C. Wang (from UCSB), and Prof. David Z. Pan (from University of Texas at Austin) respectively, in the ITC-Asia’18 opening session.
There are 24 high-quality technical papers, which were deliberately selected from 52 ITC-Asia’18 submissions based on peer reviews, and presented at eight ITC-Asia’18 regular paper sessions. In addition, the Program Co-Chairs and Industry Session Chair organized 14 Invited Talks in parallel sessions, six in two special sessions on hardware security and automotive test and reliability respectively, and eight in two industrial sessions. These 12 sessions constitute parallel sessions on 8/16 and 8/17 afternoons.
The plenary panel of ITC-Asia’18 was held in the morning of August 17. Dr. Xinli Gu (from Huawei Technologies) organized and moderated the panel with the topic: Machine Learning, a buzzword for Test Community? Five panelists, Harry Chen (Mediatek), Cheng-Wen Wu (National Tsing Hua Univ.), Xin Li (Duke University), Fei Huang (Huawei Technologies), and Yu Huang (Mentor, A Siemens Business) shared their insight to this question respectively. Then the audience and panelists have active discussions for more than half an hour.
In the afternoon of August 16, after the first three parallel sessions, the attendees enjoyed the social event, which included the city mark touring, a tour to the Manchurian Tiger Park and a one-hour acrobatics show. After that, the attendees returned to the Sun Island Garden Hotel to have the banquet. The next ITC-Asia was announced at the banquet by Prof. Seiji Kajiwara (Kyushu Institute of Technology, Japan).
ITC-Asia’19 will be held in Tokyo, Japan, on Sept. 3-5, 2019. Welcome!
2018 Posters
/0 Comments/in Headlines /by Ron PressWe have a set of 31 interesting and diverse posters for you this year. Posters present a nice information opportunity to discuss various works with the authors.
The poster session will be in the exhibit area on Wednesday from 12:00 – 2:00 PM.
Poster Listings
[154] Patrick Chen (Intel Corporation, Taipei Taiwan) and James Grealish (Intel Corporation, Hillsboro OR U.S.A). IEEE 1149.1-2013 Intel Product Compliance and Industry Enablement Plans.
Abstract. This poster is to update current Intel product 1149.1-2013 compliance status and plans to enable industry including vendors and customers
[155] Michele Portolan (TIMA), Riccardo Cantoro (Politecnico di Torino), Ernest Sanchez (Politecnico di Torino) and Matteo Sonza Reorda (Politecnico di Torino). A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks .
Abstract. IEEE 1687 introduces several novelties, like Reconfigurable Scan Networks, which offer important advantages but can result in extremely complex integrity tests. In this poster we present an innovative functional approach.
[156] Thomas Klotz (Hochschule Rosenheim) and Martin Versen (Hochschule Rosenheim). Interpreter of MATLAB/Simulink MAT-Output Files for use as Test and Verification Stimulus for Verilog Simulations with Cadence NCSim.
Abstract. A test circuit is implemented in Verilog with MathWorks’ HDL Coder. An interpreter converts the signal states to a Verilog stimulus. After Cadence import, the design is simulated with NCSim.
[157] Kalpana Senthamarai Kannan (Grenoble-INP/TIMA), Michele Portolan (Grenoble-INP/TIMA) and Lorena Anghel (Grenoble-INP/TIMA). Run-Time Aging Prediction Through Machine-Learning .
Abstract. Recent technologies are extremely sensitive to aging, and a-priori margin estimation is difficult and imprecise. The method we propose allies embedded monitors and machine learning to predict aging during runtime.
[158] Ernst Wahl (HiTestWare LLC). New Standard Test Interface Language (STIL) Applications.
Abstract. Publication of Standard Test Interface Language (STIL) for Test Flow Specification (IEEE Std. 1450.4-2017) facilitates new applications for the STIL family of standards such as tester-independent IC test program specification.
[159] George Lawton Iii (Lawton software llc). Dynamic Cloud-Based Data Collection System.
Abstract. A schema-less cloud-based distributed data collection system with dynamic validation and comprehensive system status and alerting provided a reconfigurable data collection system to solve evolving incoming data schemas.
[160] Darshal Patel (AMD) and Khushboo Agarwal (AMD). Layout aware wrapper for IP cores.
Abstract. SOCs are built up of multiple embedded cores with test wrapper around them. This poster describes methodology to use physical location and functional testcase requirements to build wrapper chains.
[161] Jeff Rearick (AMD), Al Crouch (Amida), Martin Keim (Mentor, A Siemens Business), Michael Laisne (Dialog Semi) and Glenn Colon-Benet (Intel). IEEE P1687.1: Extending 1687 to non-TAP Interfaces.
Abstract. This poster describes the work of the IEEEP1687.1 Working Group toward developing a standard for accessing on-chip instruments through a 1687 network connected an interface other than the IEEE1149.1 TAP.
[162] Anthony Coyette (ON Semiconductor), Ronny Vanhooren (ON Semiconductor), Wim Dobbelaere (ON Semiconductor), Baris Esen (Katholieke Universiteit Leuven), Nektar Xama (Katholieke Universiteit Leuven), Jhon Caicedo (Katholieke Universiteit Leuven) and Georges Gielen (Katholieke Universiteit Leuven). Visually-enhanced Dynamic Part Average Testing.
Abstract. In this work, a method is presented which combines the data from the visual inspection of wafers and the Dynamic Part Average Testing algorithm applied to the specifications.
[163] Jungho Kang (Samsung Electro-Mechanics) and Kyungsoo Chae (Samsung Electro-Mechanics). Non-Contact Probing for Electrical Connectivity of Printed Circuits.
Abstract. This study proposes a new non-contact test solution for printed circuit boards. The experiment shows that common circuit pattern defects such as open, short, and via open can be detected.
[164] Jim Johnson (SiliconAid Solutions), Alfred Crouch (Amida) and Bill Atwell (SiliconAid Solutions). IJTAG Security.
Abstract. This poster will show several security vulnerabilities and possible ways to mitigate these issues within an IJTAG network. Different levels of security will be shown meet specific device requirements.
[165] Jim Johnson (SiliconAid Solutions), Alfred Crouch (Amida) and Bill Atwell (SiliconAid Solutions). IEEE 1687 (IJTAG) Evolution.
Abstract. Poster shows the evolution of IJTAG. How IJTAG fits with other major standards for a total solution. The addition of IEEE 1687.1 and 1687.2 will enhance the solution even more.
[166] Rene Krenz-Baath (HSHL). Concurrent IJTAG.
Abstract. In this work we are proposing a novel partitioning concept to a reconfigurable test infrastructure in order to enable an independent operation of different sections of the test infrastructure.
[167] Jeffrey Hung (Microsoft) and Vidya Neerkundar (Mentor, A Siemens Business). Are You Really Testing Your Memory? Automating Test and Verification of All Memory Functionality.
Abstract. The MBIST flow is augmented by leveraging advanced tool features to automate test and verification of both the memory core and peripheral timing/power controls typically ignored by traditional models.
[168] Jeff Rearick (AMD), Steve Sunter (Mentor, A Siemens Business) and Vladimir Zivkovic (Cadence). IEEE P1687.2: Extending 1687 to Analog Circuits.
Abstract. This poster describes the status and plans of the IEEE P1687.2 Working Group toward its goal of enabling analog tests to be retargeted via IEEE1687 mechanisms.
[169] Karthik Subramanian (Ambarella), Praveen Jaini (Ambarella), Adrian Arozqueta (Mentor, A Siemens Business) and Mohammed Abdelwahid (Mentor, A Siemens Business). In-system and Manufacturing Test Flow for Large Automotive ICs .
Abstract. a DFT architecture and supporting flow addressing the challenges for large automotive chip is proposed based on an industrial flow example including challenges and trade-off to reduce design cycle cost.
[170] Xijiang Lin (Mentor, A Siemens Business) and Sudhakar Reddy (University of Iowa). On Generating Fault Diagnosis Patterns in the Presence of Xs.
Abstract. For logic diagnosis, we show that earlier methods may generate invalid tests to distinguish pairs of faults in the presence of unknowns. A method to generate valid tests is proposed.
[171] Vidya Achari (Texas Instruments Inc.) and Saminah Chaudhry (Texas Instruments Inc.). Enabling High Quality Silicon with Collaboration of Post Silicon Validation and Systems.
Abstract. Poster on Validating device smartly while improving quality by collaborating with system engineers to define the system-level tests, push validation beyond the limits, define spec compliance and automate datasheet generation.
[172] Stacy Ajouri (Texas Instruments) and Dennis Foreman (Texas Instruments). Tester Board tracking system using Streaming RITdb.
Abstract. This poster will present an application using IOT methodology to track and analyze the movement of tester boards as well as provide real time feedback to the test operation.
[173] Jon Ferguson (Graphcore), Paul Freeman (Graphcore), Paul Hudson (Mentor, A Siemens Business) and Lee Harrison (Mentor, A Siemens Business). ATE Not Required: A Complete Test Solution to Accelerate First Silicon Shipping of a Large AI Design.
Abstract. We demonstrate a fully automated test execution solution that is centered on SiliconInsight. We brought up all DFT patterns very fast, and were shipping first die samples ahead of schedule.
[174] Vidya Neerkundar (Mentor, A Siemens Business) and Ron Press (Mentor, A Siemens Business). Effective Testing of Identical Hierarchical Cores.
Abstract. This poster explains upfront design planning, combined with optimized compression architecture within the hierarchical core(s) that helps benefit from better resource utilization at the chip-level.
[175] Tal Kogan (Intel) and Amihay Rabenu (Inetl). Optimal SCAN Vector Count.
Abstract. A novel approach for finding the optimal SCAN configuration is introduced, minimizing the vector count at SoC level. This will lead to minimized overall Test time and Memory footprint.
[176] Anne Meixner (The Engineers’ Daughter LLC), Salem Abdennadher (Intel), Stepen Sunter (Mentor, A Siemens Company) and Peter Sarson (Dialog Semiconductor). What’s up with Analog Test Coverage?: IEEE P2427 IEEE Working Group Progress.
Abstract. Draft standard has been produced that includes: state-of-the-art in analog fault simulation summary, an extensive set of concise definitions, and rules for clear reporting on analog defect and fault coverage.
[177] Marvin Yang (Advantest), Alex Fan (Advantest Inc.) and Ashley Huang (Advantest Inc.). An improvement of routability of memory test interface board by auto pin assignment algorithm.
Abstract. This paper is to introduce an auto pin assignment algorithm to improve the routability of memory test interface board design.
[178] Juan Pulido Sanchez (ON Semiconductor) and Rahul Singhal (Mentor, A Siemens Business). TAP based Scan Testing of High Performance Image Sensor Chip.
Abstract. The poster show an implementation of TAP based scan-testing implementation to standardize DFT pin methodology for On-Semiconductor’s chip. Test coverage of 98.9% stuck-at and 87% at-speed testing was achieved.
[179] Hans Martin von Staudt (Dialog Semiconductor). Error Sources to Trim Distributions.
Abstract. This poster approaches the mathematical description of process variation to the trim distributions. The use of self-trim techniques shapes the resulting trimmed distributions significantly but it doesn’t change the width.
[180] Kevin Fan (Advantest Taiwan Inc). Discrete-Time Controller Implementation for Automotive High Reliability Testing.
Abstract. This paper specific challenges related to automotive device high reliability requirement,performance evaluation by FVI16 with Digital Feedback Loop capability to assure quality of test and achieve 13% test time improvement.
[181] Jackie Cooper (Intel). Method to Measure and Improve Toggle Coverage During High Volume Quick Kill Stress.
Abstract. This poster presents a method to calculate toggle coverage using customization options in Mentor’s commercial ATPG solution and shows how coverage can be improved during stress 10-15%.
[182] Rahul Singhal (Mentor, A Siemens Business), Imtiaz Ahmed (Qualcomm Technologies, Inc.) and Subhash Baraiya (Qualcomm India Private Limited). Low Pin Count Testing of an Industry Transceiver Chip.
Abstract. This solution shows low pin count testing implementation of an Industry transceiver chip using Embedded Deterministic Test (EDT)
[183] Vidya Achari (Texas Instruments Inc.), Sandeep Achari (Soliton technologies Inc) and Vishnuprasad Narayanan Kutty (soliton technologies inc). Influence of Machine Learning on Post Silicon Validation & Analysis.
Abstract. This poster discusses use of Machine Learning techniques to reduce the engineering effort in analyzing data and Test-time reduction by highlighting the potential risks earlier, derived from previous device data.
[184] Hyung Soon Kim (Samsung Electronics), Shin Ho Kang (Samsung Electronics) and Gyu Yeol Kim (Samsung Electronics). Efficient Rising Time Measurement through a Level TPD technique by using TDR Function of Automatic Test Equipment.
Abstract. This paper suggests a new measurement technique dubbed as Level TPD which efficiently measures the rising time of transmission lines, employing Time Domain Reflectometry of Automatic Test Equipment.
[185] Michael Laisne (Dialog Semiconductor), Luiz Razera (Dialog Semiconductor), Hans Martin von Staudt (Dialog Semiconductor), Bindhu Vasu (Dialog Semiconductor) and Doru Cioaca (Dialog Semiconductor). Novel IJTAG and IJTAG.1 Architecture Alternatives.
Abstract. This poster presents some novel approaches to IJTAG and IJTAG.1 architectures including an instrument interface capable of controlling the scan chains depending on the instrument state and other unique features.
ITC program
/0 Comments/in Headlines /by Ron PressThere are a few special features this year such as a shared session with ISTFA. Here is an overview of the ITC program – PROGAM SUMMARY
ITC 2018 features 41 regular paper presentations.
ITC 2018 also features a two-and-half day AI theme track with several sessions dedicated to AI. These sessions are tutorial oriented, covering a variety of AI topics and applications. The AI theme program will be available in early August.
ITC 2018 further features a one-day track on Hardware Security with 4 sessions, a one-day track on Automotive with 3 sessions, and several other invited industrial sessions. The detail of the program will be available in early August.
Papers and details of the program
A view of the papers is available through easychair. However, it is only preliminary so the times, rooms and schedule may change. This gives you a look at the papers within the program.
2018 ITC program sneak peak
Watch for a notification through twitter or on the ITC Facebook page.
Posters
Tutorials
You can select tutorials to participate in that occur prior to ITC during registration. Here is a list of available tutorials. More details are in the tutorials link under program in the main menu.
ITC India 2018
/0 Comments/in Headlines /by Ron Press2018 ITC India
ITC India preview in the news and summary of event. Number of registrations has increased significantly from 2017. There are 100+ fellowship attendees (students/faculty from academia, being sponsored by Industry). We have 12 booths from sponsors and exhibits, with exciting demos on display. ITC India will host all attendees for a networking dinner, along with cultural evening.
Conference Highlights
Keynotes from Global Technical Experts in the Test arena
6 Tutorials from Industry/Academia (Day 1)
2 days of Technical Program (8 sessions, 24 papers)
Panel discussion, Demo, Booth/Exhibits and Networking
Sessions on emerging est needs for Artificial intelligence, Automotive and IoT, Hardware security, System test, Analog and mixed signal test, Yield learning, Test analytics, Test methodology, Benchmarks, Test standards, Memory and 3D test, Diagnosis, DFT architectures, Functional and software-based test.
2018 ITC in Phoenix
/in Headlines /by Anne GattikerJoin us in 2018 ITC in Phoenix Arizona at the Phoenix Convention Center. Hotel reservations can be made from the “register” link in the main menu.
ITC will be co-located with ISTFA in 2018.
We will take advantage of sharing in some activities between our two conferences. Co-location provides some great benefits to the attendees:
Network with almost two thousand attendees
Shared keynote and select parts of the technical program
See over 150 solutions providers on the shared exhibit floor
Registration option for access to both conferences
See more on the Phoenix Convention Center and interesting nightlife
Gerald W. Gordon Award
/0 Comments/in Headlines /by Ron PressITC Is Now Accepting Nominations for the 2018 Gerald W. Gordon Award for Student Volunteerism
The International Test Conference (ITC) , the Test Technology Technical Council and the IEEE Philadelphia Section sponsor the Gerald W. Gordon Award. The award to the recipient consists of complimentary tutorial registration for one morning and one afternoon tutorial for each of the 2 days they are offered, complimentary full conference registration for ITC, complimentary registration for one of the at conference workshops, up to $750 for travel expenses to the conference and free lodging for the nights of attendance.
Eligibility Requirements
The Gerald W. Gordon Award recipient must be a student in good standing at an accredited university or college. Award recipients must have done volunteer work for one or more IEEE conferences, symposia, workshops and/or organizations dedicated to the development of electronics design and testing fields.
Consideration shall be given to the amount of volunteer service given; the breadth of volunteer service given; the impact of the volunteer service give; and worthiness of the candidate.
Nomination Process
The form for nominating a candidate can be obtained by clicking on the following link, “2018 Gerald W. Gordon Award Nomination form”. The nominator must complete and submit an application form to summarize why the applicant is qualified for the award and list the relevant service work. In addition, the nominator must identify 2, but not more than 5 endorsers. The nominator must inform the endorsers that they need to email an endorsement of the candidate as described on the nomination form. The nomination form and endorsement emails should be sent to Kenneth Mandl at mandlken@aol.com and Yervant Zorian at Yervant.Zorian@synopsys.com. No later than September 24, 2018. All candidates will be notified of the selection decision by October 1, 2018.
Machine Learning during testweek
/0 Comments/in Headlines /by Ron PressThere is a big growth in the application of machine learning to electronics test. You can see below that there are many topics related to machine learning. Some really interesting applications.
Will the singularity take over test?
Sunday Tutorial:
Tutorial 3: Learning Techniques for Reliability Monitors, Mitigation and Adaptation
Tutorial 6: Machine Learning for Test & Test for Machine Learning
Monday Tutorial:
Tutorial 9: From Data to Actions: Applications of Data Analytics in Semiconductor Manufacturing & Test
Technical Sessions:
Special Session on Machine Learning:
Paper S4.1: The Emerging Applications of Machine Learning in Testing
Paper S4.2: Enhanced Lithographic Hotspot Detection Through Design of Experiments
Paper S4.3: Opportunities in Machine Learning and Test
Also see:
Paper 2.3: Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
Paper 9.1: Kernel-based Clustering for Quality Improvement and Excursion Detection
Paper 12.1: Automated Die Inking: A Pattern Recognition-based Approach
Paper 12.3: ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation
Paper 13.2: Changepoint-based Anomaly Detection in a Core Router System
Paper 13.3: Symbol-based Health-Status Analysis in a Core Router System
Paper 14.3: Some Considerations on Choosing an Outlier Method for Automotive Product Lines
Panel P3: Yield Learning at the Crossroads – Test Chips to the Rescue?
DATA Workshop – Machine Learning Day (Friday, Nov 2nd):
Keynote on Machine Learning, presented by Siemens
Talk 1: Machine Learning – Analog Test, ChoonWee Koay
Talk 2: Machine Learning – Synergy, Sam Joneidi
Talk 3: Machine Learning – Diagnosis, presented by CMU group
Talk 4: Machine Learning – Wafer Application, presented by UT-Dallas group
Talk 5: Machine Learning – System Test, presented by Duke group
Talk 6: Machine Learning – Production Yield, presented by UCSB group
Talk 7: Machine Learning – Security, Al Crouch