ITC 2020 Now Taking Place Virtually

The safety and well-being of all conference participants is our priority. After evaluating the current COVID-19 situation, the decision has been made to transform the in-person component of ITC into an all-digital conference experience – ITC will now be an online event. Therefore, ITC will no longer take place in Washington, DC and will instead take place virtually. The conference dates remain the same – November 3-5, 2020. Proceedings will not be cancelled, and publications will continue as planned. For questions, contact itc-web@ieee.org.

Poster templates

The 2020 ITC call for papers submission site is open.  You can submit your posters through the easychair link.

There are templates and additional information available on the website program page “quick links” on the right of the page.

Poster submissions

Authors are  invited to submit a single-page poster proposal.  Here is a poster template and example.  Note that you submit the one-page extended poster abstract using the poster template.  Once accepted, then you prepare the poster itself for the conference.

  • Poster abstract submission deadline: Aug 7
  • Author notification: TBD

 

 

Paper Submission Extension

 We have had many submissions to ITC this year so far, but the difficulties of collecting data during the pandemic has led to multiple requests for extensions.  Due to these extraordinary circumstances, and to give everyone sufficient time to submit the best paper possible, the final ITC paper submission deadline will be May 29th.  This deadline is firm.  Notification of paper acceptances will be moved to July 15th  July 24th to give time for a thorough review process. 

 In addition, although we are still planning to safely hold ITC in-person in November, please do not let potential travel/health restrictions prevent you from submitting a paper now.  Authors who have such restrictions in the Fall are encouraged to contact ITC when the time comes to find an acceptable solution that will allow them to present their paper.

 

Jennifer Dworak

ITC 2020 Program Chair

 

 

ITC mobile app & photos

We received very nice feedback on the ITC mobile app.  If you haven’t already completed the mobile app survey (from within the app) then please do so because your feedback is valuable to us.

There are lots of photos within the mobile app that you can download.  You can also download any of the discussions.  The mobile app will stay active for six months after the conference.

The winner of the photo contest was Mr. Makoto Eiki with the most likes on the mobile app for this nice sunset photo.

There are also a few hundred photos from a professional photographer which you can access with this link on dropbox – https://www.dropbox.com/sh/3eicrfi13zk1cow/AAD9N8ok25blbPfJY6dIvYLva?dl=0.

We plan to use the mobile app again next year.  Here is a nice summary of frequently asked questions from the app how-to guide – link

Thanks for participating in ITC and thanks for you feedback.

Ron Press

2019 ITC Marketing Chair

2019 ITC Awards

2018 Ned Kornfield Best Paper

“Fast and accurate linearity test for DACs with various architectures using segmented models”
Shravan Chaganti, Abalhassan Sheikh, Sumit Dubey, Frank Ankapong, Nitin Agarwal and Degang Chen.
(Iowa State University)

2018 Honorable Mention

“Concept Recognition in Production Yield Data Analytics”
Matt Nero, Jay (Chuanhe) Shan, Li-C Wang
(University of CA, Santa Barbara)

TTTC Lifetime Contribution Medal

M. Ray Mercer

 

 

IEEE Fellow 2019

Anne E Gattiker
IBM, Austin, Texas

TTTC Bob Madge Innovation Award

 

Peter Maxwell
On Semiconductor

 

G.W. Gordon Student Service Award

Jay (Chuanhe) Shan

University of California at Santa Barbara

Air Force Supply Chain Provenance Challenge

AFWERX CHALLENGE at International Test Conference, November 12-14, 2019

AFRL and AFWERX have partnered to launch the Supply Chain Provenance Challenge geared around demonstrating solutions that help solve the current microelectronic supply chain problem. The challenge is attempting to identify solutions that are non-destructive in nature and prove provenance and suitability for military use of microelectronic parts in commercial off the shelf hardware to be used on base installations or in operation.

Attend this special event on the ITC Exhibit floor, booths 509, 511, & 513.

Participants

There are three participant teams

  1. BATTELLE, DPMG, KBSI
  2. Brunel University London, Supply Dynamics
  3. Object Security, Riverside Research

 

 

 

 

Sponsored by:

Air Force Research Lab (AFRL), Under Secretary of Defence for Research and Engineering, Cisco, & Nvidia

Global Test Forum

As part of its 50th anniversary celebration, ITC is proud to announce a unique and informative venue: The ITC Global Test Forum (GTF), which honors the geographic breadth of the test community and highlights the global reach of ITC during the past 50 years.

This Forum features contributions of prominent test technology related conferences and workshops established around the globe in the past 50 years. This Forum will be held as a special village at the 50th ITC Atrium just outside the exhibition hall. It consists of a circular set of stands/booth representing the participating conferences. Each participating conference will be assigned a dedicated stand/booth with a large monitor, to be used for an interactive presentation about their conference, covering the past achievements, present activities and future opportunities.

Participating in the Global Test Forum are:

In addition to the interactive presentation, each conference will be requested to publish a 4‐page paper about the corresponding conference covering past, present and future. Each conference could be represented by delegates.

On Tuesday, Nov. 12 at 2pm, the GTF unveiling ribbon cutting ceremony will take place to start interactive presentations. As the exclusive GTF supporter, the Chinese Academy of Sciences has kindly agreed to contribute towards the realization of this special GTF village.

#itctestweek #50ITC #ART #ATS #AQTR #CTC  #CSIT  #DATE  #DDECS  #ETS  #EWDTS  #HOST  #IOLTS  #ITCAsia  #ITCIndia  #IVSW  #MECO  #MTV  #NATW  #VTS

ITC 2019 Posters

ITC 2019 is pleased to present over fifty posters covering new research and industrial practices in test.  The poster session presents a unique opportunity for presenters and attendees to engage one-on-one in in-depth discussions of subjects that range from practical case studies to the first look at cutting edge “works in progress.”

Topics of this year’s session encompass all areas of test—from advances in ATE and Board Test, to Test Standards, to on-die test and DFT circuitry, to the use of machine learning and artificial intelligence in test.  Test for automotive and safety-critical devices is well-represented, along with test specifically focused on RF, Analog, and Mixed-Signal devices.

No matter your interests or background, the ITC poster session is a great chance to ask questions, learn new test methods and applications, and make new connections with colleagues.

 

ATE, Board Test, and FPGA-based Test

  • “Challenges in Industrializing high integration devices (CPU/FPGA) that has very large digital test content with EOL exceeding 25 years,” Vinayaka Lg and Prashanth Kudva
  • “Utilizing FPGA as Synthetic Instruments for Test Reuse,” TM Mak, Neil Jacobson and Louis Ungar
  • “Industrial Practices – Short Paper: Dynamic Temperature Range test and validation strategy for embedded designs and IP blocks,” Tudor Secasiu, Nancy Wang-Lee and Jihad Abbas
  • “In Test Flow Neural Network Inference on the V93000 SmarTest Test Cell Controller,” Makoto Eiki, Keith Schaub, Ira Leventhal and Brian Buras
  • “CloudTestingTm Service Enables Board Level Post Silicon Debug,” Reju Radhakrishnan, Alok Kashyap, Satish Panigatti, Yasuji Oyama and At Sivaram
  • “New FPGA Firmware for Multi-Para Probe Card Relay,” Kisub Lim
  • “High-Volume Consumer Devices Need High-Voltage Test Solution,” Anthony Lum, Bin Wang, Rohit Waikar and At Sivaram
  • Characteristics of Ring Oscillators Considering FPGA structure,” Yukiya Miura and Kouhei Sato

 

DFT and BIST

  • PS-XLBIST: Per-Shift X-Tolerant Logic BIST,” Peter Wohl, John Waicukauski and Frederic Neuveux
  • A novel PRPG streaming scan test optimized for failure analysis of field returns,” Shinobu Okanishi, Kazuki Shigeta, Satoshi Tanaka, Hiroyuki Osawa, Ric Dokken and Hiroshi Yanagita
  • “A DFT Scheme for Fault Monitoring in STT-MRAMs,” Govind Radhakrishnan, Youngki Yoon and Manoj Sachdev
  • “Custom Point Tooling for ASIC DFT Structural Checking & Test Deliverables,” Douglas Sprague, Howard Druckerman and Chris Le Coz
  • “Optimized Memory BIST solution for testing CAMs,” Dongkwan Han, Yoseop Lim, Benoit Nadeau-Dostie, Etienne Racine and Raghav Mehta
  • “High-Performance Memory BIST Solution for Testing HBM DRAMs,” Dongkwan Han, Hyeonuk Son, Etienne Racine, Raghav Mehta and Harshitha Kodali
  • `On-Chip Test Decompression and Compaction for EDT using Neural Networks,” Philemon Daniel, Aakash Tyagi, Shaily Singh, Garima Gill, Anshu Singh Gangwar, Ganesh Bargaje and Kaushik Chakrabarti
  • “Running In-System MBIST by reusing ATE MBIST tests,” Weili Wang
  • “Performance Analysis and Optimization of Reconfigurable Scan Network Architecture”, Jan Burchard, Reinhard Meier, Stephan Eggersglüß

 

Hierarchical Test and Test Standards

  • “Direct Application of IEEE 1450.4 Test Flow on ATE,” Ric Dokken
  • “Internal I/O Testing: Definition, Solution and a Case Study,” Sreejit Chakravarty, Fei Su, Indira A Gohad, Sudheer B Bandana, B S Adithya and Wei-Ming Lim
  • “Novel IEEE 1687-Like Architectures,” Michael Laisne
  • “IEEE P2654 System Test Access Management,” Jan Schat, Heiko Ehrenberg, Bradford van Treuren and Ian McIntosh
  • “Hierarchical DFT Flow mixed with a Traditional DFT Flow,” Jeongmi Kwon, Ron Press, Dongkwan Han and Juhee Han
  • “Efficient Specifications, Implementation & Tracking of IJTAG (IEEE1687) TDRs,” Chandra Nalage and Vidya Neerkundar
  • “Hierarchical Test with TAP based Silicon Defect Screening,” Satish Panigatti, Rahul Singhal, Varun Rajagopal and Knut Mellenthin
  • “IJTAG (IEEE 1687) Evolution Status,” Jim Johnson, Alfred Crouch and Bill Atwell

 

High Quality Test, Safety, and Yield

  • “Machine Learning Driven Throughput Optimization of Volume Diagnosis Methodology,” Robert Redburn, Sameer Chillarige, Nicholai L’Esperance, Jeff Zimmerman, Adisun Wheelock, Anil Malik, Martin Amodeo, Atul Chhabra and Bharath Nandakumar
  • “Overcoming Challenges in Maximizing Yield with Memory Repair,” Praveen Raghuraman, Vaishnavi Sundaralingam and Bharath Vojjala
  • “Framework for Efficient Software Test Library Development for Embedded Core with ASIL-B/SIL-2 Target,” Ashish Vanjari, Bharat Rajaram and Salvatore Pezzino
  • “Anatomy of an in-die tester to improve Safety, Infant Mortality and System Availability,” Sreejit Chakravarty, E Brazil, Rakesh Kandula, Neel Shah, V. R. Sarath, Rajeev Katta, A Karthika and Veeresha Bevinamatti
  • “DfT and Functional Safety – often friends, but sometimes rivals,” Jan Schat, Robert Jin, Lei Ma and Andres Barrilado
  • “Wafer Level Stress – Enabling Zero Defect for Automotive Microcontrollers without Package Burn-In,” Chen He and Yanyao Yu
  • “Driving Towards Zero Defects in the Next Generation Automotive Markets,” Stephen Traynor
  • “How use of guardband limits effects production quality in automotive segment and at which cost,” Gianluca Basile and Chuck Carline

 

Machine Learning, Simulation, and Modeling

  • “A Comparsion of ML Categorization Techniques for Test Datalogs,” Lawrence Luce
  • “UltraFlex AI chip final test design and challenge: A case study,” Steve Huang, Ci Kuo, Cheng-Cheng Chen and Stockton Chiang
  • “Deep Learning Based Test Compression Analyzer,” Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar Reddy, Chun-Cheng Hu and Chong-Siao Ye
  • “On Scalable GPU-based Parallel Logic Simulation,” Liyang Lai, Qiting Zhang, Hans Tsai and Wu-Tung Cheng
  • “SAL: Function Search Attack On Logic Locked Circuits,” Yuqiao Zhang, Pinchen Cui, Ziqi Zhou and Ujjwal Guin
  • “Case Study on Test Strategy of an AI SoC,” Haiying Ma, Rui Guo, Quan Jing, Jing Han, Yu Huang, Rahul Singhal and Wu Yang
  • “Wire Length as a Function of Fan-Outs,” Kazuhio Iwasaki
  • “Applying Artificial Neural Networks to Test-point Insertion: Delay Fault Coverage and Training Circuit Generation,” Spencer Millican, Yang Sun, Soham Roy and Vishwani Agrawal
  • “Enabling DFT and Fast Silicon Bring-up for Massive AI Chip – Case Study”, Hui King Lau, Jon Ferguson, Evan Griffiths, Rahul Singhal, Lee Harrison

 

RF and Analog Test

  • “High Speed RFADC/RFDAC Test Challenges for ATE,” Kevin Fan
  • “Enhanced Limited Pin Test for Analog: “Towards IEEE1687 for Analog,” Mahmoud Abdalwahab, Tom Waayers and Willy Slendebroek
  • “Sense Amplifier Offset and Weak Cell Test Considerations for Low-Voltage SRAMs,” Derek Wright, Manoj Sachdev and Dhruv Patel
  • “Photovoltaic-Powered Contactless Scribe-Line Testing with VLC Downlink and IR-UWB Uplink,” Anıl Özdemirli, Ali Arda Yıldız and Uğur Çilingiroğlu
  • “Test item reduction using machine learning in RF semiconductor production,” Ahreum Lee and Taesup Moon
  • “An Effective INL Test Methodology For Low Sampling Rate and High Resolution Analog-to-Digital Converter,” Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Haruo Kobayashi, Kazumi Hatayama, Takayuki Nakatani, Anna Kuwana, Jiang-Lin Wei, Nene Kushita, Hirotaka Arai and Lei Sha
  • “Adaptive RF DIB Design for Bench and ATE,” Gowrishankar Ilankumaran, Srinivasan Chandrasekaran and Jagadish Chandrasekaran
  • “Multi-Site DUT to Tester Interfacing for mmWave Devices,” Michael Dewey, David Hu and Dale Johnson