Paper submission site open

The 2018 ITC call for papers submission site is now open.  Submit your paper abstract by March 23rd, 2018.

You can submit your papers or posters through the easychair link.

There are templates and additional information available on the website program page “quick links” on the right of the page.

Paper submissions

Paper submissions must include:

  • Title of paper.
  • Name, affiliation, e-mail address of each author.
  • The corresponding author(s). ITC will communicate with the corresponding author(s).
  • One or two topic(s) from the topic list, or a description of your topic.
  • An electronic copy of a complete paper up to 10 pages, or an extended summary up to six
    pages. Submissions less than four pages are rarely accepted.
  • An abstract of 35 words or less to be entered online.

Submit at –

  • Paper title/abstract due: March 23, 2018
  • Paper final PDF due: April 6, 2018
  • Author notification: June 1, 2018
  • Final manuscript due: August 3, 2018

Poster submissions

Authors are also invited to submit a single-page poster proposal.

  • Poster submission deadline: June 15, 2018
  • Author notification: July 13, 2018



2018 Phoenix

Join us in 2018 ITC in Phoenix Arizona at the Phoenix Convention Center.


ITC will be co-located with ISTFA in 2018.

We will take advantage of sharing in some activities between our two conferences.  Co-location provides some great benefits to the attendees:

  • Network with almost two thousand attendees

  • Shared keynote and select parts of the technical program

  • See over 150 solutions providers on the shared exhibit floor

  • Registration option for access to both conferences




See more on the Phoenix Convention Center and interesting nightlife

Machine Learning during testweek

There is a big growth in the application of machine learning to electronics test.  You can see below that there are many topics related to machine learning.  Some really interesting applications.

Will the singularity take over test?

Sunday Tutorial:

Tutorial 3: Learning Techniques for Reliability Monitors, Mitigation and Adaptation

Tutorial 6: Machine Learning for Test & Test for Machine Learning

Monday Tutorial:

Tutorial 9: From Data to Actions: Applications of Data Analytics in Semiconductor Manufacturing & Test

Technical Sessions:

Special Session on Machine Learning:

Paper S4.1: The Emerging Applications of Machine Learning in Testing

Paper S4.2: Enhanced Lithographic Hotspot Detection Through Design of Experiments

Paper S4.3: Opportunities in Machine Learning and Test

Also see:

Paper 2.3: Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective

Paper 9.1: Kernel-based Clustering for Quality Improvement and Excursion Detection

Paper 12.1: Automated Die Inking: A Pattern Recognition-based Approach

Paper 12.3: ITC-India Best Paper: Cognitive Approach to Support Dynamic Aging Compensation

Paper 13.2: Changepoint-based Anomaly Detection in a Core Router System

Paper 13.3: Symbol-based Health-Status Analysis in a Core Router System

Paper 14.3: Some Considerations on Choosing an Outlier Method for Automotive Product Lines

Panel P3: Yield Learning at the Crossroads – Test Chips to the Rescue?
DATA Workshop – Machine Learning Day (Friday, Nov 2nd):

Keynote on Machine Learning, presented by Siemens

Talk 1: Machine Learning – Analog Test, ChoonWee Koay

Talk 2: Machine Learning – Synergy, Sam Joneidi

Talk 3: Machine Learning – Diagnosis, presented by CMU group

Talk 4: Machine Learning – Wafer Application, presented by UT-Dallas group

Talk 5: Machine Learning – System Test, presented by Duke group

Talk 6: Machine Learning – Production Yield, presented by UCSB group

Talk 7: Machine Learning – Security, Al Crouch

Successful ITC-Asia Sept 13-15

The 1st IEEE International Test Conference in Asia

(ITC-Asia 2017)

Taipei, Taiwan

(Co-Located with SEMICON Taiwan)

September 13-15, 2017

(Program Highlights)1 Panel, 4 Keynote Speeches, 3 Half-Day Tutorials, 3 Embedded Tutorials, more than 10 Invited Talks from Industry, and 28 State-of-the-Art Technical Papers.


The entire technical program is available at


Heterogeneous Integration – Design and Test Challenges Organized by Prof. Cheng-Wen Wu

(Keynote Speeches)

Keynote 1: Hardware Security – Verification, Test, and Defense Mechanisms-       Prof. Tim Cheng (Hong Kong U. of Science and Technology)

Keynote 2: Convergence of Electronic and Semiconductor Systems, and Its Impact on Testing Technology – Dr. Ishih Tseng (Chroma ATE Inc.)

Keynote 3: Seven Major Trends that are Changing how we Test ICs-       Dr. Phil Nigh (GlobalFoundires)

Keynote 4: Test Emerging Memories-       Dr. Robert Aitken (ARM Research) We sincerely look forward to your participation,

Best Regards,

Steering Committee Chair:  Cheng-Wen Wu

General Co-Chairs:  Kuen-Jong Lee and Li-C. Wang

Program Chair:  Shi-Yu Huang

Workshops for 2017

IEEE Computer Society Test Technology Technical Council Workshops

Thursday and Friday

General Workshop Information

Two workshops are being held in parallel immediately following ITC 2017. They start with an opening address on Thursday afternoon, November 2, followed by a technical session. A reception for all workshop participants will be held on Thursday evening. The remaining the technical sessions will be held on Friday, November 3. The technical scope of each workshop is described below.


Workshop Registration

All workshop participants require registration. To register in advance for one of the workshops, do so online. Otherwise, register on-site at regular rates during Test Week at the ITC registration counter. Admission for on-site registrants is subject to availability. Discount workshop registration rates apply until October 1, 2017. See the registration page for details. Workshop registration includes the opening address, technical sessions, digest of papers, workshop reception, break refreshments, continental breakfast and lunch.


Digest of Papers

A digest of papers will be distributed only to attendees at the workshops as an informal proceedings.


Workshop Schedule

Both workshops will adhere to the same schedule:


            Thursday, November 2                Friday, November 3
Registration 2:00 p.m. – 7:00 p.m. Registration 7:30 a.m. – 10:00 a.m.
Opening Address 4:00 p.m. – 4:30 p.m. Technical Sessions 8:00 a.m.  –  4:00 p.m.
Technical Session 4:30 p.m. – 6:30 p.m.
Reception 7:00 p.m. – 9:00 p.m.


                      Note: Workshop schedule is subject to change


Further Information

For more information on the two workshops contact their organizers by e-mail or check the TTTC Web site or see the ITC web workshop page.


Scope: The ART workshop focuses exclusively on test and reliability of automotive and mission-critical electronics, including design, manufacturing, burn-in, system-level integration and in-field test, diagnosis and repair solutions, as well as architectures and methods for reliable and safe operations under different environmental conditions. With increasing system complexity, stringent runtime requirements for functional safety, security and cost constraints of a mass market the reliable operation of electronics in safety-critical domains is still a major challenge. The ART Workshop offers a forum to present and discuss these challenges and emerging solutions among researchers and practitioners alike. The scope of the workshop includes, but not limited to:

  • Functional Safety in automotive domain
  • Validation of automotive systems
  • Aging effects on automotive electronics
  • Automotive standards and certification
  • Power-on & Periodic Self-test
  • High quality test and DPPB
  • Robustness and Security in Automotive


General Chair: Yervant Zorian,

Program Chair: Paolo Bernardi,


  • DATA: IEEE International Workshop on Defect, Adaptive Test, Yield and Data Analysis

Scope: In test, we use data every day. Yield data, throughput data, statistical data, reliability data, outlier data, general production data are all in everyday use. However, data means much more than that. Advances in our industry allow data from wafer fab to be reused in studying system level test results. Field failure studies now routinely uses wafer probe data to understand root cause. Data has now become a product life cycle requirement—cradle to grave. Today access to the data has become an issue; the control and sharing of data among business partners. How to efficiently process data to extract the golden nuggets of useful information amid the gigabytes of unimportant noise remains a focus and a challenge for test professionals. Workshop topics to include:

  • Data storage and security
  • Analog fault modeling & coverage
  • Adaptive test for product engineers
  • Data mining methods for test data processing
  • High/low voltage and stress testing
  • Yield learning and analysis
  • Fault localization and diagnosis
  • Product and project case studies
  • Advanced DPPM reduction techniquew


General Chair: Jeff Roehr,

Program Chair: Wesley Smith,



Great success at ITC India

ITC India was held in Bangalore with great success from July 9-11.




See details from the conference at their web site.