Industry Test Challenges Meeting
The Industry Test Challenges meeting at the International Test Conference (ITC@ITC) is an event that has been led by Phil Nigh for many years as a side gathering on Monday of Test Week. Despite Phil’s retirement, but with his ongoing support, we are continuing this tradition but elevating it to be a formal part of the ITC program and moving it to Sunday to become the official kick-off of Test Week. The nature of the meeting will remain the same as always: we’ll invite industry luminaries to present data, share challenges, and lead discussions in an informal way (i.e. no published papers, no peer review, no requirement to share slides, and plenty of open-ended back-and-forth with the audience). This meeting has a long history of being the place where emerging topics get their first discussion, where new industry directions gather momentum or get rejected, and where new ideas can be vetted in front of a community of experts who collectively represent all the disciplines within our field. As an audience member, you are expected to ask tough questions and share your insights.
To maintain the character of the meeting, the number of participants will be limited to approximately 100-150, and since this is a formal part of the program you’ll want to register early. If you have a topic that you are interested in presenting it, please reach out to the ITC committee to make a proposal.
I am interested in reconnecting with this forum after several years.
It would great to have you! It’s an incredible opportunity to engage with other thought leaders across academia and industry! See you there!!
Great to keep the momentum going!
Aiming to be at this! Phil, please will you be there ?!
Hi Paul,
I’m setting up an agenda / presentations / speakers, but I’m not sure if I will attend. (not affiliated — no travel budget)
If you attend — would you be willing to help by participating in a panel session on defects, test coverage, fault models, SDC failures, functional vs. structural test & detection. I have about 3 people lined up (including TSMC, Broadcom, hopefully Intel, AMD, …) and you’d be a good addition. (or just participate from the audience)
Thanks,
Phil
I will be interested to attend this and learn or share what industry is solving !
Looking forward to joining this call again. Is there a formal page to sign up for the industry test challenges meeting?
Hi Bradley, sign up is one of the options in the conference registration
Agenda update:
I have about 3/4ths of the agenda defined. In the next few days, I’ll send out a list of participants & titles/abstracts.
We have talks related to:
Test coverage/escapes/functional vs. structural testing
this should be a combination of a couple of presentations —
and a panel-type session where we get 5-6 people from industry to answer questions from the audience
Silent Data Corruption failure descriptions and root cause
Heterogeneous Integration test case study & in-field testing
Data Analytics — for test optimization and yield learning
Also, in-field monitoring and End-to-End correlation analysis
(hopefully). AI and test program development
Historically, we have set the final agenda until the last couple of weeks — so this is normal.
We often get some of the best talks from people who commit just before the meeting.
Thanks,
Phil
Industry Test Challenges — Agenda
“Test Challenges and Direction in the Age of AI Everywhere” — Harry Chen and Anti Tseng, Mediatek
What types of defects escape structural testing — and then fail in Data Centers? (including paretos of failures)
“Call to Action” — what actions should the industry be taking ?
“Marginal defects — how are they driving system/in-field failures?”
“SLT — why do we need SLT to detect these failures in addition to ATE/ATPG testing?”
Examples of “shifting from traditional test workflows to adaptive AI-driven systems”
“Monitoring in-Field Product Chip Health with In-die Quality Monitors” — Andrzej Strojwas, PDF Solutions Inc
Monitoring Product chip degradation and aging across the entire lifecycle
Applications: Automotive and Data Centers Products
PDF CV Core: a complex IP block embedded into a product chip design
Multiple sensors with a central control hub: Mechanical Stress Sensor, Process/Device Centering Sensor Device Reliability Sensor
Implemented in the commercial products such as ADAS
“AI Everywhere, Judgment Nowhere? What the Test Floor Still Knows” — John O’Donnell of yieldHUB
Panel Discussion: “Test Analytics: Why Is Industry Adoption Still Lagging When Product Complexity, Quality Requirements, and Field Reliability Risks Are Increasing So Rapidly?”
Moderator Ira Leventhal who is the lead of the HIR (Roadmap) chapter on Data Analytics & Adaptive Test.
Panelists will include experts from PDF Solutions, yieldHUB, Advantest, .. and 2-3 others companies.
· How heterogeneous integration, chiplets, advanced packaging, and AI accelerators are fundamentally changing analytics requirements.
· Silent Data Corruption and other field reliability challenges, and the need to correlate field failures back to manufacturing and test data.
· Why data silos, traceability gaps, incompatible data formats, security concerns, and organizational barriers continue to limit adoption.
· What types of data should realistically be shared across the semiconductor value chain, and what collaboration models are needed
among foundries, OSATs, device companies, and hyperscalers.
· AI hype versus practical production deployments. Where is AI delivering measurable results today, and what foundational infrastructure is still missing?
· Whether the biggest challenge is analytics itself, or the underlying infrastructure required for data collection, alignment, traceability, and secure sharing.
“The Role of Agentic AI in Test Program Development” — Brian Buras of Advantest
“Ai Processors — Emerging changes to Test/DFT/In-field testing through Heterogeneous Integration”, Saket Goyal, Broadcom
· Example XPU design. (2.5D, 3D)
· Unique DFT requirements. (e.g., chip-to-chiplet)
· Test Flow methods & content — how does it change with Heterogeneous Integration ?
· HBM testing — what is needed from HBM supplier related to Test ?
· In-field test requirements (ATPG or functional test, test port)
· Optimization of Test among all test steps
Data Center: Debug & Cost Challenges — Darshan Kobla, Microsoft
Advanced packaging and chiplet-based architectures are becoming foundational to high-performance computing. This shift increases the complexity and cost of testing, debugging, and failure analysis in data centers. This presentation explores these challenges in today’s data center systems. It also examines total cost of ownership (TCO) and the balance between cost and quality. Finally, it calls for industry-wide collaboration on error-data collection, analysis, and actionable insights.
Presentation related to SDC, Marginal Failures, Reliability Direction — David Lerner, Intel
Remaining Time — Panel session on:
Silent Data Corruption — what are new results related to root causes ?
fault model requirements for advanced technologies (2nm and lower) — Cell Aware …. or something else ?
unique failure/defect behaviors? Functional vs. Structural testing new methods related to reliability defect acceleration (models, burn-in??)
test time is exploding — what can be done ?
SLT — required after ATE/ATPG tests ?
Panelist list isn’t confirmed. We should have experts from Intel, Microsoft, Mediatek, Broadcom, AMD … and maybe 1-2 others.
The slides of the presentation “Test Challenges and Direction in the Age of AI Everywhere” can be found on LinkedIn at https://lnkd.in/p/gQRzbjg7