2026 Keynotes and Visionary talks
Keynote
David Greenhill
VP Silicon Engineering, Cerebras
Title: Testing Wafer-Scale AI Compute
Biography: David Greenhill has over 30 years’ experience designing high-performance computing systems. Currently he is VP of silicon engineering at Cerebras Systems Inc. His team develops all aspects of the wafer scale engine from architecture through to productization and test. Previously he has worked on the Inmos Transputer, Sun Microsystems server CPUs, Texas Instruments OMAP processors and Altera/Intel FPGAs.
Abstract: The rapid growth of generative AI is reshaping the requirements for semiconductor systems. Trillion parameter large language models, AI reasoning, and Agentic AI push the need for very fast inference. The Cerebras Wafer Scale Engine (WSE) demonstrates a radically different approach: treating an entire silicon wafer as a single 46,225 mm2 chip, integrating 4 trillion transistors and almost a million AI-optimized cores into one tightly coupled compute fabric.
Keynote
Omer Dossani
VP Global Test Services, Amkor
Title: Advanced Packages, AI & Amkor: The OSAT Test Perspective
Biography: Omer Dossani heads Global Test Services at AMKOR. His brings 30+ years of semiconductor test experience to this role. Prior to AMKOR, Omer has led Test BUs at two OSATs. His strengths are in AI test enablement in HVM environments. In his role at AMKOR he helps customers new to manufacturing successfully go through the COT process.
Abstract: Artificial Intelligence (AI) and High-Performance Compute (HPC) is driving an insatiable Assembly Packaging and Test Services OSAT demand. Amkor will be presenting the OSAT perspective of the AI & HPC market segment. Production test times at every test insertion is on the rise. Multi-Chiplet advanced packages have their unique challenges and these are compounding the thermal-mechanical package performance. Wafer level and package level test access constraints and the need for DfT enhancements to simplify the production workflow, and hence the cost are warranted.
Keynote
Aish Dubey
Vice President & Head of the SoC Div, Renesas Electronics
Title: Automotive Chiplets: Testing the Seams That Hold AI-Driven Vehicles Together
Biography: Aish has been working in the semiconductor industry for 20 years – building high-performance processing products for automotive and industrial markets. These products are powering automotive safety solutions in 100s of Millions of cars – saving lives and delivering in-cabin comfort. The key strategic area of interest for Aish is to build solutions that deliver a next generation of high-end premium safety and comfort experiences – that scale to mainstream markets – in collaboration with a broad eco-system spanning across automotive industry. Aish’s personal technology intent is to build – an easy to deploy, full stack safe & reliable platform for AI powered, software defined vehicles of the future. Aish has 20+ patents in his focused areas of engineering interest.
Abstract: Every chiplet architecture makes the same bet: that the seams between dies won’t become the system’s weakest link. As AI reasoning and autonomous driving push compute and memory demands beyond what monolithic silicon can economically deliver, hitting both an economic wall in yield and a power wall in logic-to-memory data movement, chiplets offer a way out by disaggregating the SoC into smaller, mixed-process dies stitched together over high-speed interconnects. The tradeoff is a new set of failure modes at exactly those seams: signal integrity loss, thermal stress, and power-delivery coupling between adjacent dies.
In this keynote, Renesas will make the case for chiplets as the right architecture for automotive AI, and detail the test strategy built to back that bet.
Automotive raises the stakes further. A vehicle platform must operate reliably for ten to fifteen years under ISO 26262 functional safety requirements, a timeline that moves far slower than the AI silicon evolving inside it, and a single known bad die discovered post-assembly can scrap an otherwise-good package. Traditional tests, built for monolithic parts, don’t capture these multi-die interactions.
