2026 Keynote & Visionary talks - International Test Conference

2026 Keynotes and Visionary talks

Tuesday Keynote (9:30 AM)

Omer Dossani

VP Global Test Services, Amkor

Title: Advanced Packages, AI & Amkor: The OSAT Test Perspective

Biography: Omer Dossani heads Global Test Services at AMKOR. His brings 30+ years of semiconductor test experience to this role. Prior to AMKOR, Omer has led Test BUs at two OSATs. His strengths are in AI test enablement in HVM environments. In his role at AMKOR he helps customers new to manufacturing successfully go through the COT process.

Omer started his career at Cirrus Logic and has held Engineering management positions at Cirrus Logic, Maxim and Applied Materials. Omer has a Bachelors in Electrical Engineering from UT Austin as well as a Masters in VLSI Manufacturing and an MBA from UT Austin

Abstract: Artificial Intelligence (AI) and High-Performance Compute (HPC) is driving an insatiable Assembly Packaging and Test Services OSAT demand. Amkor will be presenting the OSAT perspective of the AI & HPC market segment. Production test times at every test insertion is on the rise. Multi-Chiplet advanced packages have their unique challenges and these are compounding the thermal-mechanical package performance. Wafer level and package level test access constraints and the need for DfT enhancements to simplify the production workflow, and hence the cost are warranted.

Wednesday Keynote (9:00 AM)

Aish Dubey

Vice President & Head of the SoC Div, Renesas Electronics

Title: Automotive Chiplets: Testing the Seams That Hold AI-Driven Vehicles Together

Biography: Aish has been working in the semiconductor industry for 20 years – building high-performance processing products for automotive and industrial markets. These products are powering automotive safety solutions in 100s of Millions of cars – saving lives and delivering in-cabin comfort. The key strategic area of interest for Aish is to build solutions that deliver a next generation of high-end premium safety and comfort experiences – that scale to mainstream markets – in collaboration with a broad eco-system spanning across automotive industry. Aish’s personal technology intent is to build – an easy to deploy, full stack safe & reliable platform for AI powered, software defined vehicles of the future. Aish has 20+ patents in his focused areas of engineering interest.

Abstract: Every chiplet architecture makes the same bet: that the seams between dies won’t become the system’s weakest link. As AI reasoning and autonomous driving push compute and memory demands beyond what monolithic silicon can economically deliver, hitting both an economic wall in yield and a power wall in logic-to-memory data movement, chiplets offer a way out by disaggregating the SoC into smaller, mixed-process dies stitched together over high-speed interconnects. The tradeoff is a new set of failure modes at exactly those seams: signal integrity loss, thermal stress, and power-delivery coupling between adjacent dies.

In this keynote, Renesas will make the case for chiplets as the right architecture for automotive AI, and detail the test strategy built to back that bet.

Automotive raises the stakes further. A vehicle platform must operate reliably for ten to fifteen years under ISO 26262 functional safety requirements, a timeline that moves far slower than the AI silicon evolving inside it, and a single known bad die discovered post-assembly can scrap an otherwise-good package. Traditional tests, built for monolithic parts, don’t capture these multi-die interactions.

Visionary talk – Wednesday 2:00 PM

Unni Vadakkan

Distinguished Engineer, Marvell

Title: Breaking the Thermal Barrier: Next-Generation Thermal Challenges for High-Power Semiconductor Test

Biography: Unni Vadakkan is a Distinguished Engineer and technology leader at Marvell Technology with more than two decades of experience in semiconductor, AI, cloud, and data center hardware development. A Ph.D. graduate of Purdue University, he has held leadership roles at Marvell, Microsoft, Amazon, Qualcomm, and Intel, driving innovations across the entire hardware ecosystem, from silicon and advanced packaging to manufacturing, testing, validation, systems, racks, and hyperscale data centers. Throughout his career, Unni has led large global engineering organizations and holds 22 patents and has authored 15 technical publications. His expertise includes AI infrastructure, cloud hardware, thermal management, sustainable computing, high-volume manufacturing, hardware-software integration, testing and validation, and technology strategy.

Abstract: As Al accelerators and advanced networking devices scale in power and complexity, thermal management is becoming a fundamental challenge for semiconductor test. Test conditions frequently exceed product power levels and demand capabilities that differ significantly from deployed cooling solutions. This talk explores the emerging thermal barriers created by extreme power density, multi-chiplet architectures, and large advanced packages, and discusses the innovations required in thermal control, cooling infrastructure, and mechanical interfaces to enable reliable test of future high-performance semiconductor devices.

Thursday Keynote (9:00 AM)

David Greenhill

VP Silicon Engineering, Cerebras

Title: Testing Wafer-Scale AI Compute

Biography: David Greenhill has over 30 years’ experience designing high-performance computing systems. Currently he is VP of silicon engineering at Cerebras Systems Inc. His team develops all aspects of the wafer scale engine from architecture through to productization and test. Previously he has worked on the Inmos Transputer, Sun Microsystems server CPUs, Texas Instruments OMAP processors and Altera/Intel FPGAs.

Abstract: The rapid growth of generative AI is reshaping the requirements for semiconductor systems. Trillion parameter large language models, AI reasoning, and Agentic AI push the need for very fast inference. The Cerebras Wafer Scale Engine (WSE) demonstrates a radically different approach: treating an entire silicon wafer as a single 46,225 mm² chip, integrating 4 trillion transistors and almost a million AI-optimized cores into one tightly coupled compute fabric.

The inherent advantage that 44GB of very high bandwidth on chip SRAM, tightly coupled to processing elements and low latency compute fabric enable the world’s fastest AI inference products. This keynote will explore the design, manufacture, and test of the WSE. We will explore the challenges Cerebras overcame to make this leap practical. Cerebras is the first company to solve the yield, redundancy, diagnosis, repair, burn-in, power delivery, and thermal management problems required to deliver wafer scale computing in volume production. Robust test methodologies and repair capabilities convert imperfect silicon into reliable compute capacity. Cerebras systems are now being deployed at scale by some of the world’s leading AI and cloud providers.

Visionary Talk – Thursday

Jyotika Athavale

Functional Safety Design Manager, Waymo

Title: Safe by Design in the Era of AI & AV

Biography: Jyotika Athavale is a globally recognized leader in automotive functional safety and hardware reliability, with a career spanning influential organizations in the semiconductor and autonomous vehicle industries. Throughout her tenure at Waymo, NVIDIA, Intel, and Synopsys, Jyotika has pioneered research and industrial practices that bridge the gap between silicon-level integrity and system-level safety.

A central figure in the development of global engineering standards, Jyotika has held key leadership roles within the IEEE as President Emeritus of the IEEE Computer Society and Chair of IEEE P2851 Standards, shaping the methodologies that govern modern automotive and avionics technologies. Her expertise lies at the intersection of high-performance heterogeneous computing and the rigorous demands of automotive safety standards. Today, Jyotika continues to drive the evolution of “Safety-by-Design,” ensuring that the next generation of autonomous hardware is both performant and inherently trustworthy.

Abstract: The compute demands of next-generation high-performance computing (HPC) and artificial intelligence (AI) accelerators are driving unprecedented silicon integration. This pushes ASIC architectures to complexity levels previously unseen in mission-critical applications, such as autonomous vehicles (AV).

Ensuring functional safety and hardware dependability at this scale is a formidable challenge; traditional, localized methodologies for safety analysis, fault injection, and FMEDA can no longer keep pace with heterogeneous, multi-billion transistor designs. Today, the industry is hitting a “complexity wall,” exacerbated by fragmented data formats across disparate EDA toolchains and IP blocks.

This talk explains how the high-performance silicon ecosystem can scale functional safety and dependability through standardized interoperability and advanced on-chip safety mechanisms. We will explore the critical features for building verifiably robust silicon, including In-System Test (IST) for periodic health checks, Software Diagnostic Libraries (SDL) to augment hardware self-testing, and comprehensive Silicon Lifecycle Management (SLM) to monitor device behavior from manufacturing to end-of-life. Ultimately, coupling these mechanisms with a unified data exchange format is essential to detect faults, mitigate risks, and demonstrate safety intent.

Thursday AI in Test Keynote

The inaugural AI in Test (AIT) Workshop at ITC 2026 is pleased to feature a special keynote address by Michael Campbell, Senior Vice President of Engineering at Qualcomm.

This keynote is open to the public. We welcome everyone interested in the future of AI and semiconductor testing to attend.

Title: AI: A Hero’s (Test’s) Journey

Abstract: Artificial intelligence is redefining the landscape of semiconductor engineering, creating new opportunities to address increasing device complexity, accelerating product cycles, and unprecedented growth in engineering data. This session explores the evolving role of technology, analytics, and intelligent systems in modern test and product engineering, highlighting how organizations are adapting to meet the demands of next-generation silicon development.

Attendees will gain insights into emerging industry trends, practical applications, and the changing relationship between engineers, data, and advanced computational tools. Through a combination of real-world examples and industry perspectives, the presentation examines how innovation is reshaping engineering workflows, improving operational efficiency, and enabling teams to tackle increasingly complex challenges.

Biography: Michael Campbell is Senior Vice President of Engineering for QUALCOMM CDMA Technologies, (QCT), where he leads Product and Test Engineering, Test Automation, Failure Analysis, and Yield.

Michael joined Qualcomm in 1996. At Qualcomm, Michael has led teams across multiple areas of the business including Design Automation, FA, Yield Optimization, Product Development & Test Engineering (PDTE), Foundry Semiconductor Analysis, and Quality. Since 2014 he has been driving ML & AI test optimization internally & externally with key ATE/EDA providers for value-add AI in the test world. His drive has enabled AI boxes at multiple tester companies that enable in line real time AI functions to drive and deliver improvements in test quality and cost.

During his career at Qualcomm, Michael also has brought up Design and Test facilities in Bangalore, Singapore, Taiwan, and Mexico. In his current role, he is working to change the business and supply change through changes in PDTE and FA by driving machine learning using data available from semiconductor test to train models and automate processes.
Prior to joining QUALCOMM, Michael held engineering roles at several companies, including Mostek, INMOS and Honeywell. He holds a Bachelor of Science degree in Electrical Engineering and Computer Engineering from Clarkson University.

Event Details

Date: Thursday, October 15, 2026
Time: 4:00–5:15 PM
Location: Republic ABC, Grand Hyatt River Walk, San Antonio, TX