Tuesday Plenary Keynote

Richard Rodell

Distinguished Engineer, Infineon Technologies

Title: Test Development Ecosystem – 2025 and beyond

Biography: Richard (Rick) has been in test engineering for 33 years working in multiple roles from development to VP of test engineering.   He has worked on a wide range of products from memories, phys, complex SOCs, advanced analog and RF.    His ATE experiences have been evolved from Credence, HP, Agilent, Verigy, Advantest, Teradyne and Nextest spanning a large diverse set of development environments and programming languages.

Rick is the Test Engineering Porfolio leader for Infineon’s digital, mixed signal and memory products; Driving test development methodology, platform selection, DFT alignment and general test solution definitions across the corporation.

Abstract: A look backwards and into the future about how the test development ecosystem is quicky evolving with a focus on structure, agentic/generative AI and software tooling.

Tuesday Visionary Talk

Matheus Trevisan Moreira

Tech Lead, Silicon AI Research, Reality Labs, Meta

Title: Demystifying GenAI for Silicon Design and Test

Biography:  Matheus Trevisan Moreira began his career as a professor in Brazil before transitioning to the technology industry, where he has held key technical leadership roles across startups, Apple, and Meta. He currently serves as a tech lead at Meta, driving the development of advanced silicon architectures and accelerators for AI workloads.

Matheus is the author of over 100 peer-reviewed scientific publications, holds 12 patents, and has received multiple awards from IEEE and ACM for his contributions to computing and electronic design. His current interests focus on applying AI to accelerate and optimize silicon design, and on architecting systems for next-generation AI applications.

Abstract:  Generative AI is posed to revolutionize silicon development. However, the rapid adoption of large language models, retrieval-augmented generation, and agentic systems can seem enigmatic or complex to many industry professionals. This talk aims to demystify these technologies, providing a clear, practical look at the architecture and real-world applications of GenAI-driven agentic systems for silicon workflows. We will explore how workflows can be transformed, from simple language model prompts to more advanced, integrated agent-based methods.

Through concrete industry examples, the session clarifies how GenAI accelerates innovation, streamlines processes, and enhances quality in silicon design and test. We conclude with an accessible and forward-looking perspective on GenAI’s role as a foundational technology in silicon development, and offer actionable steps toward industry-wide understanding and adoption.

Wednesday Keynote

Dr. Jeorge S. Hurtarte

Senior Director, Teradyne

Title: Test Insertions and Test Challenges for AI-HPC in CoWoS and CoPoS Advanced Heterogeneous Integrated Packages

Biography:  Dr. Jeorge S. Hurtarte is currently Senior Director and Principal Marketing Strategist in the Semiconductor Compute Test Division at Teradyne.  Jeorge has held various technical, management and executive positions at Teradyne, Lam Research, LitePoint, TranSwitch, and Rockwell Semiconductors.

Jeorge is in the Advisory Board of SEMI of North America and serves as co-chair of the IEEE Heterogeneous Integration Roadmap (HIR) Test Chapter.  Jeorge holds a PhD in Electrical Engineering, and three master’s degrees (MBA, Computer Science, and Telecommunications).  He is also visiting professor at the University of California, Santa Cruz and at the University of Phoenix.  He is co-author of the book Understanding Fabless IC Technology.

Abstract: As AI-HPC (High Performance Computing) solutions continue to evolve from single compute devices (GPUs or Switches) into advanced heterogeneous integrated packages with multiple chiplets (e.g., HBMs, GPUs and Switches with UCIe interfaces, etc.) in a silicon wafer or panel interposer (aka CoW: chip-on-wafer; CoP: chip-on-panel), and then on to the final package substrate (CoWoS: chip-on-wafer-on-substrate), the test complexity is increasing significantly, as well as the number of possible test insertions.

This presentation provides an overview of this trend and related new test challenges which also require new test strategies that will guarantee both known-good-die and known-good-CoW to optimize the overall cost of test, while maximizing the final test insertion yield and quality of the finished CoWoS device.

Thursday Keynote

Anand Joshi

Senior Technical Fellow, TechInsights

Title: Architecting the AI Silicon: The Technology, Market, and Future

Biography:  Anand Joshi is currently the Senior Fellow for AI at TechInsights. He is a semiconductor industry veteran with over 25 years of experience and a recognized expert in the AI chip community. He’s been a marketing executive and advisor with prominent AI companies that include Esperanto Technologies, NanoSemi (acquired by Maxlinear), Wave Computing, and Redpine Signals (acquired by Silicon Image).

His market research reports via Tractica/Omdia/TechInsights on computer vision, AI, and data center infrastructure have been used by Fortune 500 companies for strategic planning purposes since 2015. He is a frequent conference speaker and advises the venture community about AI chip products, strategy, and market feasibility. Anand holds an MSEE from Virginia Tech and an MBA from UC Irvine.

The chip industry is being reshaped fundamentally by the rapid evolution of AI, moving far beyond general-purpose compute that historically has been prevalent. GPUs, with their parallel processing capabilities, have become the workhorses for deep learning and the dominant compute architecture. CPUs have stagnated and the talk about specialized accelerators has become amplified. The AI technology , nevertheless, still remains in its infancy and will demand even higher performance in the future.

In this talk, we’ll take a look at the evolution of AI in its present incarnation, and how the performance needs of neural networks have driven the chip market. We’ll look at some of the key AI applications and discuss what stops them from scaling. We’ll discuss chip architectures – CPU, GPU, FPGA and ASICs – and how they relate to the needs of AI applications. We’ll look at the industry trends, key players in the market and forecast. We’ll conclude by discussing current challenges faced – performance, power, software infrastructure and scaling – and how that will shape future chip industry landscape.