2026 Tutorials (coming soon)
There is a diverse set of tutorials available to growth your knowledge and understanding.
Here is an overview of the tutorials within the program – ITC Tutorials.
For details of the various topics please enter the TTTC ITC tutorials page.
Registration is through the ITC registration page.
2026 Workshops
Workshops are available towards the end of ITC test week.
6th International Workshop on Silicon Lifecycle Management
SLM Workshop
Including ARTS – Automotive Reliability, Test & Safety
October 15-16, 2026
With increasing system complexity, security, stringent runtime requirements for functional safety, and cost constraints of a mass market, the reliable and secure operation of electronics in safety- critical, enterprise servers and cloud computing domains is still a major challenge.
There is a great need for a holistic approach for silicon lifecycle management, spanning from design time to in-field monitoring and adaptation.
The SLM Workshop offers a forum to present and discuss these challenges and emerging solutions among researchers and practitioners alike.
October 15-16, 2026
The 3D & Chiplet TEST Workshop” focuses exclusively on test of and design-for-test for three-dimensional, chiplet-based, and stacked ICs, including systems-in-package (SiP), package-on-package (PoP), 3D-Stacks based on through-silicon vias (TSVs), micro-bumps, and/or interposers.
The 3D & Chiplet TEST Workshop offers a forum to present and discuss these challenges and emerging solutions among researchers and practitioners alike.
AI in Test (AIT) Workshop
Artificial Intelligence (AI) is rapidly reshaping semiconductor test engineering. To provide a dedicated venue for the community to examine these developments, ITC 2026 is launching the inaugural AI in Test (AIT) Workshop, to be held during ITC Test Week on October 15–16, 2026, in San Antonio, Texas.
Unlike a traditional technical conference, AIT is organized around community-led workshop sessions rather than individual paper presentations. We invite the community to propose and organize 60–90 minute sessions that examine how AI may transform important areas of semiconductor test.
