Wednesday, November 1, 12:00 pm – 2:00 pm

Poster Session

PO.1: Multisite PMIC Fast Trimming with Pattern-based Search Function

Kevin Fan (Advantest, Taiwan)
PO.2: Delay Fault Testing Using Cloud Testing Service

A.T Sivaram, Oyama Yasuji (Advantest, USA)

Sam El Alam, Arul Subbarayan (Qualcomm, USA)

PO.3: Productivity Gains with Hierarchical DFT Methodology for Physically Flat Design – A Case Study

Jonathan Phelps (On Semiconductor, USA)
Vidya Neerkundar (Mentor, USA)

PO.4: Multicycle At-Speed Test

Mallika Pokharel, Duncan Walker (Texas A&M University, USA)

PO.5: The Rainbow Transformed from a Set of Uniform-Defect Wafer Maps

Ya-Syuan Wu, Ching-Ju Lin, Jwu E Chen (National Central University, Taiwan)
Hsing-Chung Liang (Hsing-Chung Liang Chung Yuan Christian University, Taiwan)

PO.6: A Method to Debug LBIST-Mode SSA/TF Silicon Failure Accurately Using Scan-Through-TAP (STT) Mode

Vinay Kumar (STMicroelectronics Inc, USA)

PO.7: A Comparator-based Method for Decomposition of Random and Data-dependent Jitter in High-Speed Data Links

Yan Duan (Iowa State University, USA)
Hsinho Wu, Masashi Shimanouchi, Mike Peng Li (Intel, USA)
Degang Chen (Iowa State University, USA)

PO.9: Transition Fault Testing for Offline Adaptive Voltage Scaling

Mahroo Zandrahimi (Delft University of Technology, Netherlands)
Philippe Debaud, Armand Castillejo (STMicroelectronics, France)
Zaid Al-Ars (Delft University, Netherlands)

PO.10: Automatic Solution to Frame-Clock-Domain Groupings for Efficient At-Speed Structural Testing

Hardik Bhagat, Greeshma Jayakumar (GlobalFoundries, India)

PO.11: A Hierarchical, Power-safe, Parallel Memory Self-Test Architecture for In-Field Test

V.R. Devanathan, Sumant Kale (Texas Instruments Inc, USA)

PO.12: Hierarchical Hybrid EDT-LBIST System

Tal Kogan,  Amihay Rabenu (Intel, Israel)

PO.13: A VMIN Temperature Shift Outlier Screen for Cold Test Elimination

Todd Jacobs, William Morris, Sharon Levy (NXP Semiconductors, USA)

PO.14: Self-Test and Self-Repair Method for FPGAs

David Keezer, Jingchi Yang (Georgia Tech, USA)

PO.15: Testing TSVs for Micro-void and Pinhole Defects Using OTA

Procheta Chatterjee, Surajit Kumar Ro, Hafizur Rahaman, Chandan Giri (IIEST, Shbpur, India)

PO.16: Development of a Production-worthy ATE Test Screen for a Unique Device Fail Signature

Mike Lemanski, Kassem Hamze, Archana Jain (NXP Semiconductor, USA)

PO.17: Online Electrical Interconnect Test Method Utilizing IEEE 1149.1 Architecture

Daisuke Yabui, Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima University, Japan)
Shyue-Kung Lu (National Taiwan Univ. of Science and Technology, Taiwan)

PO.18: BIST On-demand Using Distributed On-Chip Programmable Data Streams

Carl Wisnesky II, Patrick Gallagher (Cadence Design Systems, Inc., USA)

PO.19: Evaluation of Transition-X Fault Model for On-Chip Diagnosis of Multiple Defects

Matthew Beckler,  Shawn Blanton (Carnegie Mellon University, USA)

PO.20: Technique to Test Hierarchical Designs with Multiple Design Levels

Vidya Neerkundar (Mentor, USA)
Henrik Bergendal (MicroSemi Corporation, Denmark)

PO.21: Taming of the Shmoo

Wesley Smith, Steven McDowall (Mentor, USA)
Marc Hutner (Teradyne Inc, Canada)

PO.22: An Immodest Proposal to Bridge Test and Design Data for SoC and IP Yield

Anne Meixner (The Engineers’ Daughter LLC, USA)
Keith Arnold (PDF Solutions, USA)

PO.23: Reducing Memory BIST ATE Test Time Through a Data-ready Observation Port Modeled in IJTAG

Kaitlyn Chen, Ramesh Sharma (Intel Corporation, USA)
Luc Romain (Mentor Graphics – A Siemens Business, Canada)
Reinhard Meier (Mentor Graphics Development (Deutschland) GmbH, Germany)
Jf Cote, Benoit Nadeau-Dostie, Albert Au (Mentor, Canada)
Martin Keim (Mentor, USA)

PO.24: Scaling Interactive IJTAG Debug Beyond the Desktop to ATE

Matthew Knowles, Givargis Danialy (Mentor, USA)
Marc Hutner (Teradyne, Canada)

PO.25: Quo Vadis IJTAG.1?

Martin Keim (Mentor Graphics, USA)
Al Crouch (Amida, USA)
Michael Laisne (Dialog Semiconductor, USA)

PO.26: A Low-Cost Jitter Separation and ADC Spectral Testing Method Without Requiring Coherent Sampling

Shravan K Chaganti (Iowa State University, USA)
Li Xu (Texas Instruments, USA)
Degang Chen (Iowa State University, USA)

PO.27: Interstitial DFT in SpeedCore™

Raghuraman Rajanarayanan (Achronix Semiconductor, India)
Adam Cron (Synopsys, USA)