2018 ITC Tutorials

2018 TTTC tutorials during ITC test week.  These tutorials are taught by leading experts over two days. Catch up on the latest in an area with advanced tutorials or learn the basics.

Sunday, 10/28

Morning

Afternoon

1 Learning Techniques for Reliability Monitoring, Mitigation and Adaptation Mehdi Tahoori (Karlsruhe Institute of Technology) 4 A Test Guy’s Journey To AI Li-C. Wang (UCSB)
2 Integrated Bulk Sensors enabling On-line test for Radiation Induced Soft-Errors and Noise Sensing Frank Sill Torres (Federal University of Minas Gerais), Rodrigo Possamai Bastos (TIMA Laboratory, Université Grenoble Alpes) 5 Mixed-signal DfT & BIST: Trends, Principles, and Solutions Stephen Sunter (Mentor, a Siemens Business )
3 Targeting “Zero Defect” IC Quality: Advanced Cell Aware Fault Models and Adaptive Test Automotive Reliability & Test Strategies Adit D. Singh (Auburn University) 6 Beyond DFT: The Convergence of DFM, Variability, Yield, Test, Diagnosis and Reliability Srikanth Venkataraman (Intel Corporation), Robert Aitken (ARM)

 

Monday, 10/29

Morning

Afternoon

7 Memory Test and Repair in FinFET Era Yervant Zorian (Synopsys) 10 Automotive Reliability & Test Strategies Riccardo Mariani (Intel), Yervant Zorian (Synopsys)
8 From Data to Actions: Applications of Data Analytics in Semiconductor Manufacturing & Test Haralampos-G. Stratigopoulos (Sorbonne Universités, UPMC Paris 6, CNRS, LIP6), Yiorgos Makris (The University of Texas at Dallas) 11 Testing of TSV-Based 2.5D- and 3D-Stacked ICs Erik Jan Marinissen (IMEC), Krishnendu Chakrabarty (Duke University – Dept. ECE)
9 High-Speed I/O Testing in High-Volume Manufacturing Salem Abdennadher (Intel Corporation), Saghir A Shaikh (Broadcom Corporation) 12 From Test to Post-Silicon Validation: Concepts and Recent Trends Arani Sinha (Intel Corporation), Sandip Ray (NXP Semiconductors Inc.)

TUTORIAL SUMMARIES

1: Learning Techniques for Reliability Monitoring, Mitigation and Adaptation

Mehdi Tahoori (Karlsruhe Institute of Technology)
Abstract: With increasing the complexity of digital systems and the use of advanced nanoscale technology nodes, various process and runtime variabilities threaten the correct operation of these systems. The interdependence of these reliability detractors and their dependencies to circuit structure as well as running workloads makes it very hard to derive simple deterministic models to analyze and target them. As a result, machine learning techniques can be used to extract useful information which can be used to effectively monitor and improve the reliability of digital systems. These learning schemes are typically performed offline on large data sets in order to obtain various regression models which then are used during runtime operation to predict the health of the system and guide appropriate adaptation and countermeasure schemes.

 

2: Integrated Bulk Sensors enabling On-line test for Radiation Induced Soft-Errors and Noise Sensing

Frank Sill Torres (Federal University of Minas Gerais), Rodrigo Possamai Bastos (TIMA Laboratory, Université Grenoble Alpes)
Abstract: Integrated bulk current sensors offer a promising solution for detection of radiation induced transient faults and soft errors, substrate noise analysis, and detection of maliciously induce transient effects on secure circuits. Consequently, these Bulk Built-In Current Sensors (BBICS) are of interest for online testing as well as diagnosis purposes that explore the design’s safety and reliability. The main objectives of this tutorial are the presentation of the main concepts of integrated bulk current sensors, the discussion of design methods, and the introduction of strategies for system integration. Further aspects are a thorough analysis of radiation induced effects in current technologies, sensor testing methods, and the exploration of its applicability for on-chip noise sensing.

 

3: Targeting “Zero Defect” IC Quality: Advanced Cell Aware Fault Models and Adaptive Test Automotive Reliability & Test Strategies

Adit D. Singh (Auburn University)
Abstract: Commercial applications continue to demand ever-higher IC quality. Meanwhile, recent experience with new fault models suggests that current structural test methodologies can miss significant defectivity, resulting in increasing reliance on expensive system level tests as a final defect screen. This two-part tutorial presents a comprehensive study of known state-of-the-art techniques directed at targeting “Zero-Defect” IC quality. Part one focuses on new fault models, including the cell aware methodology, for an in-depth understanding of the actual defects in modern standard cells that are missed by conventional stuck-at and TDF tests but detected by the new fault models. Part two presents adaptive test methods that employ innovative statistical techniques to further improve test effectiveness by optimizing the tests applied to individual parts.

 

4: Machine Learning for Test and Test for Machine Learning – A Journey to AI

Li-C. Wang (UCSB)
Abstract: Applying “machine learning” (ML) for test has been a growing field of interest in recent years. Many potential applications have been demonstrated and tried. In this tutorial, I will start with a review of the basic principles for applying ML in selected test applications and highlights the key challenges. I will share the experience as how various barriers led us to prioritize those applications and identify the low-hanging fruits in wide variety choices of applications. These include barriers in data, in learning theories, in computational resources, and in competition with existing non-ML based solutions. Based on that experience, I will then try to explain what “machine learning” means in theory and in practice. Results based on actual industrial settings will be used to demonstrate the potential benefits and explain the barriers for developing a practical ML-based solution. More importantly, I will explain the fundamental difference between the “machine learning” for test and the popular machine learning employed in image/speech recognition. At the end of this journey, I will show why “applying ML in practice” in our field can actually mean to build an AI system which in principle is similar to other AI systems such as autonomous vehicles and consequently, the deployment of such an AI system will face a set of test and verification questions regarding the ML components employed in the system.

 

5: Mixed-signal DfT & BIST: Trends, Principles, and Solutions

Stephen Sunter (Mentor, a Siemens Business)
Abstract: The lack of systematic analog DFT explains why analog accounts for the majority of failures in automotive mixed-signal ICs. We’ll try to improve this situation. We first review trends in ad hoc DFT and fault simulation, IEEE 1149.1/4/6/7/8/10, and 1687, and ISO 26262, continuing on to BIST for ADC/DAC, PLL, SerDes/DDR, and random analog. Next, essential principles of practical analog BIST are presented including, for instance, addition, subtraction, and spec-based defect-oriented test, followed by practical DFT techniques, ranging from quicker analog fault coverage simulation to over/under sampling methods that greatly improve range, resolution, and reusability. We conclude with the two Analog Test Coverage and Access standards being developed by engineers from 30 companies, and measurement of related ISO 26262 metrics.

 

6: Beyond DFT: The Convergence of DFM, Variability, Yield, Test, Diagnosis and Reliability

Srikanth Venkataraman (Intel Corporation), Robert Aitken (ARM)
Abstract: The tutorial goal is to show how design for yield (DFY) and design for manufacturability (DFM) are tightly coupled into what we conventionally think of as test. As process geometries shrink, the line between defects and process variation blurs to the point where it is essentially non-existent. As feature sizes reduced, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss due to the interaction between design and manufacturing. The basics of yield and what fabs do to improve defectivity and manage yield are described. DFM techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield are discussed. In DFM/DFY circles, it is common to speak of defect limited yield, but it is less common to think of test-limited yield, yet this concept is common in DFT (e.g. IDDQ testing, delay testing). Test techniques to close the loop by crafting test patterns to expose the defect prone feature and circuit marginality through ATPG, and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact are covered. This tutorial will provide background needed for DFT practitioners to understand DFM and DFY, and see how their work relates to it. The ultimate goal is to spur attendees to conducting their own research in the area, and to apply these concepts in their jobs.

 

7: Memory Test and Repair in FinFET Era

Yervant Zorian (Synopsys)
Abstract: Recent growth in content delivery has led to an explosion in the use of embedded memories. This tutorial will present the trends and challenges of growing memory content on chip and how to ensure detection of today’s defects upon manufacturing and during life time, including process variation and FinFET specific defects including 7nm technology. BIST and Repair solutions to address debug, diagnosis, yield optimization and data retention of failure modes will be presented. Given the tens of thousands of embedded memory instances in today’s SOCs, this tutorial will also cover power management constraints, functional timing implications, test scheduling optimization, and area minimization options.

 

8: From Data to Actions: Applications of Data Analytics in Semiconductor Manufacturing & Test

Haralampos-G. Stratigopoulos (Sorbonne Universités, UPMC Paris 6, CNRS, LIP6), Yiorgos Makris (The University of Texas at Dallas)
Abstract: Throughout the design and production lifetime of an integrated circuit, a wealth of data is collected for ensuring its robust and reliable operation. Ranging from design-time simulations to process characterization monitors on first silicon, and from high-volume specification tests to diagnostic measurements on chips returned from the field, the information inherent in this data is invaluable. At the same time, the need for cost-effective solutions for various test-related tasks is becoming more pressing, especially in complex mixed-signal SoCs. As a result, using data analytics methods to mine this information and identify meaningful correlations has seen intense interest and numerous breakthroughs have been made during the last decade. This tutorial seeks to elucidate the utility of data analytics in semiconductor manufacturing and test. Relevant concepts from data analytics theory will be introduced and agglomerated with current practice, showcasing their effectiveness on actual case studies with industrial data. A comprehensive survey of the relevant literature will be provided, organized around five themes: (i) Test cost reduction through replacement of expensive tests by inexpensive alternatives and/or static elimination of superfluous tests, (ii) Adaptive test, (iii) Pre-deployment evaluation of candidate test methods through probabilistic test metrics, (iv) Post-production performance calibration through cost-effective knob tuning, (v) Yield learning and process monitoring through wafer-level spatial and lot-level spatiotemporal correlation modelling.

 

9: High-Speed I/O Testing in High-Volume Manufacturing

Salem Abdennadher (Intel Corporation), Saghir A Shaikh (Broadcom Corporation)
Abstract: With advances in VLSI technology, packaging and architecture, Systems on Chip (SoC) continue to increase in complexity. Increasing complexity has resulted in an unprecedented increase in design errors, manufacturing flaws and customer returns related to High-Speed I/O (HSIO) circuits. This tutorial presents challenges and existing techniques to meet test complexity of HSIO and methodologies needed to achieve the high-quality usually mandated by the critical applications such as automotive and medical, etc. Both the system and block level test techniques with particular emphasis on DFT/BIST based methods and their suitability to production level environment are presented in this tutorial. Additionally, this tutorial includes a section on test practices for 2.5D/3D products with IO interfaces.

 

10: Automotive Reliability & Test Strategies

Riccardo Mariani (Intel), Yervant Zorian (Synopsys)
Abstract: Given today’s fast growing automotive semiconductor industry, this tutorial will discuss the implications of automotive test, reliability and functional safety on all aspects of the SOC lifecycle, while accelerating time to market for automotive SOCs. The SOC lifecycle stages will include design, silicon bring-up, volume production, and particularly in-system test. Today’s automotive safety critical chips need multiple in-system self-test modes, such as power-on self-test and repair, periodic in-field self-test during mission mode, advanced error correction solutions, etc. This tutorial will analyze these specific in-system test modes and the discuss the benefits of using ISO 26262 including its 2nd edition (to be published in 2018), in order to ensure that standardized functional safety requirements are met.

 

11: Testing of TSV-Based 2.5D- and 3D-Stacked ICs

Erik Jan Marinissen (IMEC), Krishnendu Chakrabarty (Duke University – Dept. ECE)
Abstract: After a long period of technology hype, finally real 3D-stacked ICs containing through-silicon vias and micro-bumps (and also their interposer-based 2.5D-SIC variant) are hitting the market. Testing of 2.5D- and 3D-SICs is fraught with new test and design-for-test challenges, for which solutions are only emerging. The test challenges are the following. (1) Test flows: what to test for when? (2) Test content: do these stacked ICs bring new defects and faults and how do we test for those? (3) Test access: how do we pump in/out the test stimuli/responses into the dies and die stacks? In this tutorial, we present test flow cost modeling and optimization, advances in 3D probe technology, advanced 3D-DfT architectures and optimization, and the latest details of the ongoing IEEE Std P1838 standardization effort for test access.

 

12: From Test to Post-Silicon Validation: Concepts and Recent Trends

Arani Sinha (Intel Corporation), Sandip Ray (NXP Semiconductors Inc.)
Abstract: The tutorial will provide a comprehensive overview of post-silicon validation, from readiness and planning to execution. The diverse activities involved in enabling the validation on modern System-on-Chip design at various phases of the system life-cycle will be covered, and the conflicts, cooperation, and trade-offs will be discussed. The trade-offs span a vast spectrum of activities, including security, power management, and physical design, and we will provide an overview of its complexity as well as industrial best practices. We will describe how we can leverage of the design for test infrastructure for post-silicon validation, and the collaboration areas between validation and test. We will cover several instrumentation, control, and observability technologies including tracing and triggering, scan dumping, and off-chip transport mechanisms.