Tuesday October 31, 4:30 pm – 6:00 pm

Session S1: Special Session, Benchmarks – Room 202 A/B


Jeff Rearick (AMD, USA)

S1.1:  A/MS Benchmark Circuits for Comparing Fault Simulation, DFT, and Test Generation Methods

Stephen Sunter (Mentor, Canada)
Peter Sarson (ams, Austria)

S1.2: Doing More with ITC2016 IEEE 1687 Benchmarks: Ecosystem and PDLs

S. Devadze, A. Tsertov, Artur Jutman (Testonica, Estonia)
Jeff Rearick (AMD, USA)

S1.3: A Third of a Century of ATPG Benchmarks

Scott Davidson

Session S2: Special Session: Design to Specifications and Test for Defects in Analog – Room 203 A/B


Rubin Parekhji (Texas Instruments (Bangalore), India)

S2.1: Testing for Latent Defects in the Analog: Does the Spec. Matter?

Wim Dobbelaere (ON Semiconductor, Belgium)
S2.2: Functional vs. Defect-based Testing in Context of Analog Mixed-Signal Blocks

Mike Ales (Texas Instruments, USA)

S2.3: Advanced Test Methods for Mixed-Signal Circuits: Specification vs. Defect-based Test

Abhijit Chatterjee (Georgia Tech, USA)

Session TC: IEEE TTTC E.J. McCluskey Best Doctoral Thesis Award 2017: Final Competition –  Room 201 C


Michele Portolan (IMAG, France)
TC.1: Fault-tolerant Electronic System Design
Boyang Du, Luca Sterpone (Politecnico di Torino, Italy)
TC.2: Accurate and Robust Spectral Testing with Relaxed Instrumentation Requirements
Yuming ZhuangDegang Chen (Iowa State University, USA)
TC.3: Design-for-Test and Test Optimisation for 3D SOCs
Surajit Kumar Roy (Indian Institute of Engineering Science and Technology, India)

Session TUT1: Advances in Diagnosis in Nano-scale Era – Room 201 A/B

Manish Sharma (Mentor Graphics, USA)
TUT1.1: Diagnosis Part 1
Shawn Blanton (CMU, USA)
TUT1.2: Diagnosis Part 2
Enamul Amyeen (Intel, USA)
TUT1.3: Diagnosis Part 3
Srikanth Venkataraman (Intel, USA)