Tuesday, October 31, 2:00 pm – 4:00 pm

Session 1: Analog/RF BIST & Calibration – Room 201 A/B

Gordon Roberts (McGill University, Canada)
Haralampos-G. Stratigopoulos (Sorbonne Universités,)
1.1: Low-Cost Dynamic Error Detection in Linearity Testing of SAR ADCs
Nimit Jain (IIT Madras, India)
Nitin Agarwal, Rajavelu Thinakaran, Rubin Parekhji (Texas Instruments, India)
1.2: Concurrent Built-in Test and Tuning of Beamforming MIMO Systems Using Learning-assisted Performance Optimization
Sabyasachi Deyati, Barry Muldrey, Abhijit Chatterjee (Georgia Tech, USA)
Byunghoo Jung (Purdue University, USA)
1.3: An On-Chip ADC BIST Solution and the BIST-enabled Calibration Scheme
Xiankun Jin (NXP Semiconductor, USA)
Tao Chen (Iowa State University, USA)
Mayank Jain, Arun Kumar Barman (NXP semiconductors, India)
David Kramer, Doug Garrity (NXP Semiconductors, USA)
Randal Geiger, Degang Chen (Iowa State University, USA)
1.4: Built-in Self-Test for Stability Measurement of Low-Dropout Regulator
Jae Woong Jeong, Ender Yilmaz, Leroy Winemberg (NXP Semiconductors, USA)
Sule Ozev (Arizona State University, USA)

Session 2: Diagnosis – Room 202 A/B

Ken Butler (Texas Instruments, USA)
2.1: Diagnosing Multiple Faulty Chains with Low-Pin Convolution Compressor Using Compressed Production Test Set
Subhadip Kundu, Kuldip Kumar, Rishi Kumar (Synopsys, India)
Rohit Kapur (Synopsys Inc., USA)
2.2: Test Reordering for Improved Scan Chain Diagnosis Using an Enhanced Defect Diagnosis Procedure
Srikanth Venkataraman (Intel Corporation, USA)
Irith Pomeranz, Shraddha Bodhe (Purdue University, USA)
Enamul Amyeen (Intel, USA)
2.3: Systematic Defect Detection Methodology for Volume Diagnosis: A Data Mining Perspective
Chuanhe Shan (University of California Santa Barbara, USA)
Pietro Babighian, Yan Pan, John Carulli (GLOBALFOUNDRIES, USA)
Li-C. Wang (University of California Santa Barbara, USA)
2.4: High-Throughput Multiple Device Diagnosis System
Sameer Chillarige, Anil Malik, Sharjinder Singh, Joe Swenton, Krishna Chakravadhanula (Cadence Design Systems, India)

Session 3: Scan Architectures Room 201 C

T.M Mak (self, USA)
Mehdi Tahoori (Karlsruhe Institute of Technology, Germany)
3.1: Frequency-Scaled Segmented (FSS) Scan Architecture for Optimized Scan-Shift Power and Faster Test Application Time
Wilson Pradeep, Prakash Narayanan, Rajesh Mittal, Naman Maheshwari, Nikita Naresh (Texas Instruments, India)
3.2: Maximizing Scan Pin and Bandwidth Utilization with a Scan Routing Fabric
Grady Giles, Jeff Rearick (AMD, USA)
Guoliang Li (AMD, China)
John Schulze, Yan Dong, James Wingfield, Tim Wood (AMD, USA)
3.3: On Applying Scan-based Structural Test for Designs with Dual-Edge Triggered Flip-Flops
Xijiang Lin (Mentor Graphics Corp., USA)
3.4: Analysis and Mitigation of IR-Drop-Induced Scan Shift-Errors
Stefan Holst (Kyushu Institute of Technology, Japan)
Eric Schneider (University of Stuttgart, Germany)
Koshi Kawagoe (Kyushu Institute of Technology, Japan)
Michael A. Kochte (University of Stuttgart, Germany)
Kohei Miyase (Kyushu Institute of Technology, Japan)
Hans-Joachim Wunderlich (University of Stuttgart, Germany)
Seiji Kajihara, Xiaoqing Wen (Kyushu Institute of Technology, Japan)

Session PO: Poster Previews Room 202 C/D