Thursday, November 2, 2:00 pm – 3:30 pm

Panel 2: Hot Topic Virtual Panel – What does the Test Community really think about System-Level Test? – Room 201 A/B

Moderator:
Paul Berndt (Test Consultant, USA)

System Level Test is becoming a bit of a hot button topic at times. The general sentiment with some is, “hate to have to implement System-Leve Test, but cannot live without it”. In this “virtual panel” everyone can weigh in during this interactive session and share their opinion through the audience poll. We will see what the Test community sees as the issues and challenges going forward. We will raise the questions one by one providing some time for the everyone to answer in an online poll and then show the results real-time.

Panel 3:  Yield Learning at the Crossroads – Test Chips to the Rescue? – Room 202 A/B

Panel Organizers:

Enamul Amyeen, Shawn Blanton

Moderator:

Enamul Amyeen

Current approaches for test chip design does not fully reflect all the complexities of actual customer product ICs, therefore yield learning is becoming more dependent on product fails as opposed to test chips. The capability of a test chip to capture real product issues may be diminishing as we move further and further into advanced process nodes. Are test chips missing the mark, or is the fabrication process simply different when customer ICs are manufactured?

Panelists:

Rob Aitken, ARM

Shawn Blanton. CMU

Rao Desineni, Global Foundries

Doug Gerwitz, Intel

Bruce Cory, NViDIA

Mike Bourland, Qualcomm

Panel 4: Automotive Test and Reliability: Challenges or Opportunities – Room 202 C/D

Panel Organizer:

Yervant Zorian, Synopsys,

Moderator:

Yervant Zorian, Synopsys

While ensuring automotive test quality needs (DPPB) and meeting reliability levels and functional safety standards are major challenges today, could our embedded test and repair infrastructure become the new opportunity to address the multipurpose needs of automotive SoCs?

Panelists:

O. Ballan, Xilinx

G. Boschi, Intel

M. Casarsa, ST

C. Eyschenne, Bosch

T. Parekhji, Texas Instruments

L. Winemberg, NXP Semiconductors

 

Session S6: Special Session: Emerging IEEE Test Standards – Room 201 C

Chair:
Mike Ricchetti (Synopsys, USA)
S6.1: IEEE 1149.10-2017: Mapping JTAG and Scan onto Serial I/O Such As SERDES and SPI
CJ Clark (Intellitech, USA)
S6.2: IEEE P1687.1: Accessing 1687 Networks via Non-TAP Interfaces
Al Crouch (SiliconAid, USA)
S6.3: IEEE Analog Test Coverage and Access: A New Study Group for Longstanding Problems
Steve Sunter (Mentor, Canada)