Partner Conferences
ATE Vision 2020
http://atevision.tttc-events.org/
This workshop examined where the ATE industry is heading in the near and long-term. Moore’s law continues to move forward with denser, large, faster, and highly heterogeneous devices coming our way. Further complications to this situation are the challenges associated with multiple cores on a die and the 3D trends enabled by die-stacking and thru-silicon-vias.
These issues, when added to ever increasing Test complexity, Cost-of-Test and Time-to-Market pressures pose a significant challenge to the ATE industry. To meet these challenges the industry (ATE developers and End-Users together) need to innovate in areas such as: shared interconnect technology, streamlined test program generation methods, better integrated Design-for-Testability tools.
DATE
http://www.date-conference.com/group/date
DATE2011 will be the place to learn about the latest in the design and engineering of electronic systems and embedded software. DATE 2011 will feature two Special Days focussing on topics of outstanding importance to industry and academia and will dedicate a full-day program of keynotes, panels, tutorials and technical presentations to each of them. The special days are: Smart Devices of the Future and Intelligent Energy Management-Supply and Utilisation.
DATE has a vibrant and professional exhibition which provides excellent opportunities for close interaction between industrial and scientific research, managers, designers, developers, and others. The exhibition in Grenoble will feature a multitude of world market-leaders and numerous start-ups in the semiconductor and EDA sectors.
DFM&Y
http://vlsicad.ucsd.edu/DFMY/
Increased manufacturing susceptibility in today’s nanometer technologies requires up to date solutions for yield optimization. In fact, designing an SoC for manufacturability and yield aim at improving the manufacturing process and consequently its yield by enhancing communications across the design – manufacturing interface. A wide range of Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) methodologies and tools are proposed today. Some of which are leveraged during the back-end design stages, and others have post design utilization, from lithography up to wafer sort, packaging, final test and failure analysis. DFM can dramatically impact the business performance of chip manufacturers. It can also significantly affect age-old chip design flows. Using a DFM solution is an investment and thus choosing the most cost effective one(s) requires trade-off analysis. The workshop analyzes this key trend and its challenges, and gives the opportunity to discuss a range of DFM and DFY solutions for today’s SoC designs.
ISSCC
ISSCC is the flagship conference of the Solid-State Circuits Society and is the premier forum for presenting advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity to network with leading experts in the field. For 2011, the Conference theme is Electronics for Healthy Living, highlighting an important direction for the conference, involving integrated circuits for biomedical systems. A diverse set of exciting plenary presentations is being planned to cover the conference theme and other key trends. The Conference will feature more than 200 technical presentations representing benchmark results, design in state-of-the-art process technologies, and circuits in emerging device technologies. ISSCC 2011 will also feature a variety of educational events (tutorials, short course), advanced-circuit forums and evening sessions. We have also extended the student activities to include the DAC/ISSCC Student-Design Contest and the Student Research Preview.
ISTFA
http://asmcommunity.asminternational.org/content/Events/istfa/
Enrich your career at the 36th International Symposium for Testing and Failure Analysis, November 14-18 in Dallas, Texas. Acquire the latest knowledge from the field’s leading professionals with six days of tutorials, short courses, technical presentations, panels, and user groups. Research leading edge instruments and solutions at the industry’s largest dedicated equipment expo. Meet and network with hundreds of your peers from novice to expert.
MTDT
http://nthucad.cs.nthu.edu.tw/~mtdt09/
Following the traditions set up by its predecessors, MTDT09 provided a forum dedicated to the recent advancements of the memory technology, covering topics such as memory device, circuit design, architecture, fabrication process, verification, yield analysis testing/diagnosis/repair for all kinds of memory such as SRAM, DRAM, Flash memory, EPROM, EEPROM, embedded memories, 3-D memories, content addressable memories, etc.
SELSE
The growing complexity and shrinking geometries of modern device technologies are making these high-density, low-voltage devices increasingly susceptible to influences from electrical noise, process variation, and natural radiation interference. System-level effects of these errors can be far reaching. Growing concern about intermittent errors, erratic storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practices in system-level error management. Participants from industry and academia explore both current technologies and future research direction (including nanotechnology).
