Focus Features

Archive of ITC 2011 Focus Features

This page contains an archive of Focus Features for the 2011 ITC.

Final Week: Focus Feature on Why You Should Attend ITC.

There is only one week left until ITC TestWeek events begin. Our last Focus Feature is a good time to summarize what you can get out of ITC. There is still time to Register On-line.

Tutorials.

12 Tutorials and the second presentation of the Test Clinic on the Sunday and Monday before ITC begins can give you an in-depth, full day review of an important test topic at the basic or advanced level. Has new technology or a new project been thrown at you with no time for training? Do you want to broaden your horizons? A tutorial (or even two) will help you really understand a new area.

Panels.

Papers and presentations are carefully crafted and rehearsed You can hear what the experts think in a free-for-all environment on a panel – and hear other experts challenge them about it. And you can stand up and challenge them yourself. They’ll help you look at our field in a new way.

Keynote and Invited Addresses.

Our keynotes this year cover the future of architecture and of process technology. And our invited address, suitable to our new venue just steps from Disneyland, will take you behind the scenes of the World of Color show,

Which brings us to

Networking and Fun.

Sometimes you find out more in the hallway than you do in the hall. ITC has the densest concentration of test people anywhere. You might find someone who has solved the problem bugging you at work. You might find someone to critique your idea. You might do even better when there is beer and wine involved at the Welcome Reception. No matter – after it, you’ll get a VIP view of the World of Color spectacular.

But you can also get good information without beer on the

Exhibits Floor.

This is the place to find out about products and services which can help you do your job better, and get into discussions with the experts that exhibiting companies bring with them. For many people, exhibits are the reason to go to ITC. This year, for the first time, the exhibits are free for all three days. You can register on-site any time during ITC.

There is one downside to registering for free exhibits – you miss out on the

Technical Papers, Lecture Series, and Advanced Industrial Practices papers.

This is the heart of ITC, where you hear the latest results from industry and academia, hear solutions to problems you might be facing now or facing next year, and get an advance look at the techniques you’ll be using in the future. If you buy the Presentation CD, available only at ITC which has most of the technical presentations, you can even avoid copying the slides.
But TestWeek is not over when ITC is. There are still three
Workshops where you can hear new work on important topics in an atmosphere conducive to questions and discussion.

And after that you still have

The Disneyland and California Adventure Parks.

You can still get your room rate discount before and after TestWeek, and discount park tickets are available through our Registration Page. Yes, it is time to have fun. You deserve it.

Week Nine

Focus on the Exhibit Hall Passport

All registered ITC attendees will receive a passport with their conference tote. Get your passport stamped while visiting exhibitor booths and or corporate presentation session(s). Drop your completed passport into the box on the exhibit floor, and be eligible for daily drawings* for an Apple iPod touch and an iPod shuffle, or a Disney store gift certificate of equivalent value. Collection boxes are in the exhibit hall. The drawings will take place each day in the exhibit hall at 5:00 p.m. on Tuesday, 4:00 p.m. on Wednesday and at 12:30 p.m. on Thursday. You need not be present at the time of drawing to win. Please see the full instructions included with your passport for details.

*Apple is not a participant in or sponsor of this promotion.

Program Focus on Lecture Series and Advanced Industrial Practices Sessions

The purpose of the Lecture Series and AIP sessions is to give ITC attendees pointers they can use back at their jobs. The presentations in these sections, from leading experts, will help you do your job better.

There are no papers associated with these sessions in the Proceedings, so if you wish to get the benefit of seeing how test problems are actually solved, you need to register for and attend ITC – and to be sure to attend these sessions.

Full details are available in the ITC Advance Program. Some of the topics for 2011 are:

• Small Delay Faults

• New Developments in Boundary Scan Standards
• Electrical Validation from First Chip to Product
• Adaptive Test in Production

Back this year are the popular Elevator Talks and Partner Conference Tracks.

Week 8

ITC Tuesday Keynote Address

The 2011 Tuesday Plenary Keynote Speaker is Bill Dally, of Stanford University and Nvidia. The topic is Power, Programmability and Granularity: The Challenges of ExaScale Computing Dr. Dally is the Willard R. and Inez Kerr Bell Professor of Engineering at Stanford University and Chief Scientist at NVIDIA Corporation.

Reaching an ExaScale computer by the end of the decade, and enabling the continued performance scaling of smaller systems requires significant research breakthroughs in three key areas: power efficiency, programmability, and execution granularity. To build an ExaScale machine in a power budget of 20 MW requires a 200-fold improvement in energy per instruction: from 2 nJ to 10 pJ. Only 4X is expected from improved technology. The remaining 50X must come from improvements in architecture and circuits. To program a machine of this scale requires more productive parallel programming environments—that make parallel programming as easy as sequential programming is today. Finally, problem size and memory size constraints prevent the continued use of weak scaling, requiring these machines to extract parallelism at very fine granularity—down to the level of a few instructions. This talk will discuss these challenges and current approaches to address them.

Program Focus on the Poster Session

With the ITC paper deadline so far ahead of the conference, lots of good work gets completed too late for a regular paper. There are also some groups, such as standards groups, who wish to interact with ITC attendees in order to get feedback. The ITC Poster Session is the answer. This year the session is being held from 12 noon to 2 pm Wednesday in the ITC Exhibit Hall. Enjoy lunch while seeing some of the 29 posters in this years session. Our posters come from around the world, from many companies and universities, and cover a wide variety of topics including 3-D test, diagnosis, P1687, test compression, high volume manufacturing, and even BIST for quantum dot cellular automata.

The titles and authors of the posters (way too many to list here) can be found in the ITC Advance Program.

Week 7.

Focus on the ITC Thursday Keynote Address

We are excited to have Jyuo-Min Shyu, President of the Industrial Technology Research Institute,Taiwan (ITRI) as our Thursday Keynote Speaker. His topic is A Systems Perspective on the R&D of Industrial Technology. Scientific discoveries open up new horizons, and technologies based on them can create or transform markets. However, the process of translating scientific discoveries into technologies involves a series of risk steps, resulting in low success rates. In industrial technology research institutes such as ITRI, the planning of such projects typically starts with conceptualizing innovative applications that meet certain needs of consumers or society. Once initiated, the process is forced to be in constant touch with both ends of its range: scientific discovery and market needs; the utmost consideration is the large impact it will have on industries, economy and the society at large. In this talk, examples of industrial technology research from a semiconductor application perspective, along with the collaboration model with the industry and academia, are presented. Crucial factors leading to successful deployment of new technologies such as cost, quality, and reliability are also addressed.

Program Focus on Panels

This year ITC features four panels, spread throughout TestWeek. Panels allow industry leaders and experts to give their opinions and argue about important test topics (sometimes heatedly) and also lets the audience weigh in with their opinions.

As has now become traditional the first panel is held on Monday, before ITC formally begins. This year it is How Will Testing Change in the Next 10 Years?, moderated by Phil Nigh. Testing has changed a lot in the past ten years, thanks to new technologies, better tools, globalization, and the consolidation of the industry. The discussion will begin with each panelist answering a small set of questions, and then will move to questions solicited from the audience before the session begins, The panelists are: Ben Brown, Bruce Cory, Bill Eklow, Rohit Kapur, Bob Madge, Janusz Rajski and Jeff Rearick.

Panel 2 is Challenges and Best Practices in Advanced Silicon Debug. The fortunes of a company can ride on how fast a new product can make it from early silicon to the market. What is the best way to find and fix silicon problems: functional test on ATE, system-level test or structural test?

In the Exhibit Halls of ITCs in bygone years in-circuit testers (ICT) could be seen, simplifying board test by directly targeting manufacturing defects and simplifying test program creation. Panel 3, In-Circuit Test (ICT): The King Is Dead; Long Live the King! considers the future of ICT. Does the board test manufacturing need a new generation of board test system or does the existing In-Circuit Test (ICT) have sufficient features to test PCBAs for the next 10 years and beyond?

Our final panel, on Thursday afternoon, complements the Thursday keynote described above. Today more and more electronic manufacturing is moving to Asia. Test, as one of the important parts of the manufacturing process, is used to guarantee the product quality and manufacturing smoothness. The Gap: Test Challenges from the Asia Manufacturing Field and Today’s Tools describes the gap between the test challenges that the Asian companies are facing and the tools they have available today. The ITC audience will get an opportunity to better understand the needs for innovation in test technologies and tools.

Week 6.

Focus on Disney Imagineering

The many rides, attractions and shows in the Disneyland and California Adventure Parks must run reliably, time after time, almost every day of the year. We hope you will get a chance to visit or revisit the parks before and after TestWeek (our discounted hotel rates are good before and after the conference, and you can purchase pre-arrival discounted park tickets through the hotel reservation web page) but we know you will see one of the newest attractions, World of Color, at our private showing as the finale of our Welcome Reception.

The next day, Wednesday, September 21 a t 4:30 pm, you will get to hear how it was done, in a talk by Chuck Davis, Disney Creative Entertainment Senior Technical Director. Chuck discusses the creation of the technical aspects of the spectacular show World of Color. This invited talk will take ITC attendees on a little-seen journey through the design, fabrication, installation and mounting process of World of Color.

We will discover how the teams use normal manufacturing principles and process to insure the eventual outcome is safe, reliable, maintainable, and financially viable, while still delivering on the highest of creativity. We will see how the show starts from a creative idea, imagined to provide an “only at Disney” emotional experience. Attendees will understand how principles of high-reliability, self-diagnostics, redundancy, self-healing, safety and leveraging cutting edge technology are spun together to support the show’s creation. We will also see how these systems are used to maintain the show, as well as keep the creative vision fresh and up-to-date.

Join us for a unique talk. It night make you want to see World of Color again.

Program Focus on Microprocessor Test

Microprocessor designs stress our testing techniques to the limit. Microprocessors are faster and bigger than most designs you will see, and are often early users of new process technology. Four papers in Session 13 provide information on the latest in this field.

Transition test is a vital component of the microprocessor test suite, both for finding defects and for speed binning. But there have been concerns that transition test might fail good parts, and we are always worried about tests passing bad parts. The first paper, from Intel, desribes three DFT methods used to understand their at-speed scan, and to make sure these concerns were addressed.

While high quality at-speed test is important for quality, a chip late to market might have volume so low (or zero) to make this not an issue. The next paper, from Oracle, describes how transition test can be used to find slow paths and other problems during debug. It will challenge some of your beliefs on the benefits of transition test versus path-delay test.

A popular type of paper at microprocessor test sessions is the case study. The third paper in the session describes the DFT features of Intel’s latest Itanium Processor.

The days when we could set one voltage for each part are long past. Today, we need to decide for each individual die the tradeoff between power and speed, and set the voltage accordingly. The final paper in this session, from LSI Corporation, describes a manufacturing test flow which finds the minimum voltage while reducing test time.

Week 5.

Visit the ITC Exhibit Floor

The ITC Exhibit Floor gives you the chance to visit a broad, diverse set of EDA, hardware and test solutions providers covering almost any test need. The exhibits area will also be the site of corporate presentations that highlight new and exciting developments in test equipment, services, tools and methodologies. Visiting our exhibitors lets you get an in-depth view of their capabilities, and lets you engage in detailed discussions to determine if their products are a good match for your needs.
For a higher level view, attend the ITC Corporate Presentation Track where representatives from exhibiting companies give the highlights of their product line.

In addition, all registered ITC attendees will receive a passport with their conference tote. Get your passport stamped while visiting exhibitor booths and or corporate presentation session(s). Drop your completed passport into the box on the exhibit floor, and be eligible for daily drawings for an Apple iPod touch and an iPod shuffle, or a Disney store gift certificate of equivalent value. Collection boxes are in the exhibit hall. The drawings will take place each day in the exhibit hall at 5:00 p.m. on Tuesday, 4:00 p.m. on Wednesday and at 12:30 p.m. on Thursday. You need not be present at the time of drawing to win. Please see the full instructions included with your passport for details.

Program Focus on ATE

No matter how good your test or DFT is, you need an ATE to tell you if your part works or not, and, if not, what is wrong. Come to Session 3, ATE Feature Set Expansions and Test Cost Reduction, to learn how to use ATE in ways you might not have considered. These three papers discuss: extending the capability of ATE into areas such as highly-parallel, low-level DC measurements, development of an ATE test cell for both at-speed characterization and production testing of an 8Gb/sec ATE channel-slice ASIC, and implementation of multi-domain testing techniques to reduce test cost.

High-speed testing keeping you awake at night? The four papers in Session 11, Taming High-Speed Digital Interfaces > 10 Gbps , deal with digital testing at rates above 10 Gb/sec, and cover such topics as: methods to analyze interconnect, using AWGs to generate SATA spread-spectrum clocking, testing of devices which use multi-level signaling to increase data rates, and using the latest and greatest FPGAs to extend ATE capabilities and data rates with custom add-on modules.

Week 4

Come to a very Buggy ITC Welcome Reception

This year we take advantage of our location on the Disney Resort. The ITC Welcome Reception for 2011 is in Disney California Adventure. The evening begins in A Bugs Land, a popular attraction reserved for our exclusive use. Guests can socialize with friends old and new while enjoying food, drinks and fun elements of this attraction. The second part of the Welcome Reception will be a private showing of the spectacular World of Color, a new Disney nighttime show that premiered in June 2010. World of Color has more than 1,200 fountains and includes lights, water, fire, fog, and lasers, with high-definition projections on mist screens accompanied by musical scores. Please note that this does not include general admission to other park areas.


Photo © Disney

Each full-conference ITC attendee receives one free admission wristband to the event. For all other Test Week attendees and/or companions, the admission fee is $42 per person. Extra admissions may be purchased at the ITC registration desk.

Program Focus on Board Test

There is plenty for a board test engineer to do and see at ITC this year.

• Two board test related tutorials and a tutorial on Test Economics that will be of interest to any engineer. The Test Economics tutorial has a large section on board and system test, that will be given more time if there are more board and system test engineers attending.

• Monday night panel on How Testing Will Change in the Next 10 Years (including Board/System Test)
• Keynotes on ExaScale computing and Challenges for Asian Manufacturers (both have board and system test implications)
• Open IEEE 1149.1 working group meeting Tuesday morning right before lunch
• Tuesday afternoon session on IEEE 1149.1 and IEEE P1687
• BTTAC meeting from 4 to 5 pm
• Board test paper session and a very lively (think bar room brawl) panel session on Wednesday morning
• Poster session (including lots of board test stuff) from noon to 2:00 pm on Wednesday – lunch included
• IEEE P1687, IEEE 1581 and SJTAG open meetings on Wednesday afternoon
• IEEE P1838 (3D Test) working group meeting on Thursday morning, plus paper session on Stacked Device Test (this plays into system test)
• Testing Three Dimensional Stacked ICs Working from late Thursday afternoon through Friday afternoon

The more participation in board and system test activities there is, the more encouraged engineers will be to write more papers for next year, so come to the ITC and to the board test track.

Week 3.

Disney Institute

This year ITC offers a special opportunity: to update your creativity by attending the Disney Institute.

Disney’s founder, Walt Disney, knew that Disney’s success as a company relied on its ability to encourage innovative ideas and th en support their development. At the Disneyland® Resort, Disney not only encourages the creative process, Disney manages it to produce the maximum return on its investment.

This Program is designed to show you the business case for creativity. Disney facilitators will present the viability of a corporate culture where the creative process thrives and produces profitable products and services.

They will help you discover how organizational creativity can give you the competitive edge in today’s changing business world

You must register for this special program by August 15. Please see the Advance Program for more details on this special program, and see the Registration Page for costs.

Program focus on Defect-oriented and Power-aware ATPG

Advances in test generation and DFT highlighted at ITC over the past 35 years have meant that we hardly have to worry about traditional stuck-at coverage any more. Now we worry about whether we can detect subtle defects, sometimes hard to model, and whether our DFT will do more harm than good. Session 2, right after lunch on Tuesday, looks at these problems with three papers.

First, an embedded test often consists of a pseudo-random part followed by a deterministic part to improve coverage. If we can make the pseudo-random part more effective, we could shorten the expensive deterministic part. Pseudo-exhaustive test can do this, but test length can grow exponentially with circuit size. This paper introduces partial-pseudo exhaustive test, which can offer the best of both worlds.

A defect of great interest is the small delay fault. The next paper targets these by faster-than-at-speed test, which is accomplished by copying patterns and running them at desired speeds, masking the ends of paths which would have timing failures due to the increased speed, and shows how to minimize slack and maximize delay for the paths which are left. This increases defect coverage while reducing the number of patterns.

We must reduce the power consumed during scan test to protect our circuits and to guarantee accurate results. Independently, we must reduce power consumption in functional model, often through clock gating. These requirements have been in conflict, and we typically turn off clock gating during scan. The third paper shows how to make use of existing clock gating hardware to reduce power usage during the launch cycle of an at-speed test.

Week 2

ITC Tutorials.

In 2011 we offer 12 tutorials and the second presentation of the TTTC/TTEP test clinic. See the Advance Program for more details on each.
Our tutorials are:

1. Mixed-Signal DFT and BIST: Trends, Principles and Solutions

2. High-Quality and Low-Cost Delay Testing for VDSM Designs: Challenges and Solutions
3. Bridge to Moore—IEEE Standards Provide Access to Debug, Validation and Test of Ever More Complex ICs—On ATE, on Board, in System
4. Power-aware Testing and Test Strategies for Low-Power Devices
5. The Convergence and Inter- relationship of Yield, Design-for- Manufacturability and Tes
6. Practices in Analog, Mixed-Signal and RF Testing
7. Delay Test: Concepts, Theory andRecent Trends
8. Demystifying Board-level Test and Diagnosis
9. Testing Low-Power Integrated Circuits: Challenges, Solutions and Industry Practices
10. Statistical Adaptive Test Methods Targeting “Zero Defect” IC Quality and Reliability
11. The Economics of Test and Testability
12. Testing Memories in the Nano-Era: Fault Models, Test Algorithms, Industrial Results, BIST and BISR

Tutorials 1 – 5 are on Sunday, September 18, tutoruals 6 – 12 are on Monday, September 19.

Also on Monday is the Test Clinic: Logic and Memory Testing for SOCs. This is a full day special tutorial, particularly geared towards newcomers to the area of test, such as new test engineers and students pursuing graduate studies in test. Its key objective is to offer a broad yet comprehensive review of basic test topics in an accessible way to the lay audience.

Program focus on Diagnosis and Data Mining

Today’s failure modes are complex enough that traditional methods such as scribe-line test structure measurement, test chips and in-line inspections are no longer adequate for understanding failures. Instead, learning needs to be done on real products. In turn the results of that learning can be used to improve design, the manufacturing process and test. This year’s ITC features a session on diagnosis and data mining that includes three papers using real industrial data to do just that. Together they demonstrate test time reduction, test result prediction and IDDQ-based diagnosis. Another section on defects discusses methods to analyze and detect ever more subtle failure mechanisms including small delay defects, those related to statistical variations in lithography and those subject to enhanced screening using body bias control during test.

Week 1

Introducing: the Weekly ITC Focus Feature

Each Monday, from now until ITC opens in September, we will highlight an ITC technical program element and a Testweek element. Watch the right column of our home page itctestweek.org, or follow us on Twitter to be alerted when a new feature is posted.

ITC Focus Features for July 11, 2011.

Submit to an ITC Workshop.

Three workshops are held Thursday and Friday of Testweek. These are great opportunities to focus in on a hot topic with a relatively small (100 or so) audience of engineers with similar interests.
Submissions for the workshops are still open.

The 3D Test Workshop, which focuses on test of and design-for-test for three-dimensional stacked ICs (3D-SICs) is accepting submissions until August 1

The IEEE International Workshop on Silicon Debug and Diagnosis is the seventh of a series of highly successful technical workshops that consider issues related to debug & diagnosis of semiconductor circuits and systems – from prototype bring-up to volume production. The deadline date for SDD 2011 is also August 1.

The IEEE International Workshop on Defect & Adaptive Test Analysis (DATA-2011) will discuss new avenues of research and development in the areas of extracting information about defects and IC behavior through the use of innovative analysis techniques. Extended abstracts can be submitted until July 21.

Program focus on Analog Mixed/Signal Testing

For the first time, there will be an analog/mixed-signal DFT session every day of ITC. On Tuesday a session (Session 1) addresses DFT and test strategies for general analog, including the first paper to describe a new analog fault simulation approach with volume silicon results. On Wednesday, in Session 6 on RF DFT, we see the focus for RF shifting to how to reduce test cost the most, away from how to design for test. On Thursday in Session 16, we see for the first time, two papers on new sampling methods for analog signals.