ITC TestWeek 2008
International Test Conference 2008 was held from October 26—October 31 at the Santa Clara Convention Center in Santa Clara, California.
The 2008 technical program focused on breakthrough ideas to address the challenges of providing high-quality, cost-effective tests for IC, boards and systems and concentrated on the latest advances in such hot topics as design for manufacturability, power-aware test, recent advances in delay test, logic diagnosis, silicon debug, and high-quality test methods. The technical program offered 35 paper sessions, and was supplemented with a lecture series, advanced industrial practices sessions and a poster session. Test Week opened with 17 tutorials covering such diverse topics as high-speed interface testing, design-for-manufacturing, silicon debug and diagnosis, statistical screening, delay test, scan compression, failure mechanisms and high-quality test methods for nanometer technologies, analog mixed-signal and RF test, memory test, IEEE Std. 1500, system-in-package test, and wafer-probe.
Below find summaries of the keynote address and invited addresses.
Keynote Address: Managing Test in the End-to-End, Mega Supply Chain, Mike Lydon, Vice President, Technology and Quality, Global Supply Chain Management, Cisco
Today's connected environment has created significant growth opportunities in the electronics industry. Products have never been so diverse, ranging from phones that can play movies and give directions to "super routers" that can move terabits worth of data around the world instantly. It is now possible to access the internet from areas which once had little to no contact at all with the rest of the world. This growth in opportunities has spurred significant supply chain growth with significant growth in both consumers and suppliers. The challenges for today's supply chain have also grown significantly with much greater diversity in products; increasing customer requirements (lower cost, faster deliver, better quality and faster time-to- market); smaller, denser, faster and more complex technology and a supply chain that now consists of thousands of suppliers and thousands of customers all over the world. All of this with a totally ―virtual, global supply chain. Mike Lydon will highlight these challenges and discuss how test, and the data produced by test can either enable or disrupt these virtual supply chains. He will talk about communication in the virtual supply chain and how test can enable real time, end-to-end adjustments over the product lifecycle. Mike will conclude by presenting his vision of the test and data managed, optimized, end-to-end, global, virtual supply chain.
Invited Address: Computing at the Crossroads (and What Does it Mean to Verification and Test)?, Jan N. Rabaey, Donald O. Pederson Distinguished Professor, University of California at Berkeley
When looking back over the past six or seven decades, one can only be awed by the tremendous strides computation has made. The nature of the problems we can tackle today is truly astounding. Yet, when speculating about what the coming decades will bring, one cannot escape a perception that some fundamental changes in the computation arena are afoot. Today, we are interpreting computation as the execution of complex algorithms that are executed in sequential fashion and are bound to deliver deterministic answers. A number of factors are conspiring to fundamentally change that model, namely the scaling of technology to the nanoscale dimensions; the emergence of distributed computation and the changing nature of computation and the underlying hardware platforms from a cognitive/perceptive model to statistical model. These trends will have a profound effect on the way we verify and test designs. It is paramount that we start to explore what all of this means today if we want to be prepared for what tomorrow will bring.
Invited Address: Having FUN with Analog Test Robert A. Pease, Staff Scientist, National Semiconductor
Bob Pease is a legend in the analog design community. Bob has designed analog circuits for over 48 years, including 25 linear ICs and dozens of op amps and discrete circuits. As a designer for 48 years, Bob understands the importance of test engineers, test plans and test design. He also understands the implications of not getting the test done right. Bob will share the good, the bad and the ugly test experiences he's had over the years (in a way that only Bob can do). Bob will also answer pre-submitted questions during the session, making this the first interactive invited talk in ITC history.
Invited Address: This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company, Jeff Rearick, AMD Fellow, Mile High Design Center, AMD
As cost pressures on electronic products continually increase, the urge to trim investment in test-related circuitry, activity, and equipment increases correspondingly. Not only can this strategy backfire if taken too far, but it also ignores the opportunity for test to actually add value to products. This presentation will examine the positive role that test can play and give audience members a set of guidelines to take back to their own companies so that they can perform their own analyses. Numerous examples from a variety of different electronic industries show a wide range of possible solutions.