ITC TestWeek 2007
The 2007 International Test Conference (ITC) held in Santa Clara, CA from October 23-25, 2007 featured a Keynote Address, three Invited Addresses, seven panels, 32 paper sessions, 4 lecture series sessions, 16 tutorials and three workshops. Below, find summaries of the keynote address and invited addresses.
Keynote Address: Meeting the Challenges at the Extreme Ends of the Spectrum—Nanotechnology and Giga Complexity, Gadi Singer, Vice President, Mobility Group and Assistant General Manager, Ultra Mobility Group, Intel Corp.
Gadi Singer discussed some of the major industry trends and technology advances in VLSI IC design and test. His talk covered the market-driven need to provide PC-like complexity in consumer electronic devices, while continuing to reduce design and test cycle time and costs. He discussed the cumulative effects of ever-increasing product complexity, shrinking form-factors and process geometries, the need for low power consumption and their impact on product development methodologies. Gadi presented the "late binding" integration principle and the entailing demands on decreased product development cycle time. He provided a perspective on how these trends apply to Intel from the highest performance IA core to the lowest power IA core and highlighted some of the expected solution directions for addressing the industry challenges.
View slides of the 2007 Keynote Address (PDF file, 3.8 Mbytes).
Invited Address: Pinning Down This Elusive Thing Called "Adaptive Test," Ken Butler, TI Fellow, Product Reliability, Silicon Technology Development, Texas Instruments
Adaptive Test is one of those terms that have rapidly become trendy in test. It means a lot of things to a lot of different people. This talk examined the various ways in which adaptive test ideas have been proposed and implemented throughout the industry, several of which saw their first public disclosure at ITC. The Texas Instruments perspective on adaptive test was emphasized, particularly as it relates to outlier methods and a high volume wireless business.
Invited Address: The Need for Standard and Efficient Interconnection and Access of Embedded-Everything, Alfred L. Crouch, Chief Scientist and Director of DFT R&D, Technology Development, Inovys Corp.
There are many and varied semiconductor test, debug and diagnosis related problems that are rapidly rising in importance—no trouble found (NTF), DFM parametric-sensitive test-escapes, rising cost-of-test, complex die-stacked architectures, Network-on-chip architectures, loss of diagnostic resolution due to compression/compaction, and more. The current ad hoc solutions for these problems involve incorporating DFT logic and other additional logic—DFD, DFM, DFY—and the application of IEEE standards for control, portability and access. These forms of logic are also used in multiple test and operation environments—wafer probe, package test on ATE, in-system test and in-system operation. This has resulted in the growth of "embedded content" and the need to more efficiently include and access this content. The IEEE P1687 standard in conjunction with IEEE 1149.1 and IEEE 1500 is one part of the solution to all of these problems and targets the organization, connectivity, test scheduling, automation, and use of this embedded instrumentation.
Invited Address: What’s The Trouble with Analog/Mixed-Signal Test—Not Enough Feedback, Gordon W. Roberts, James McGill Professor of Electrical and Computer Engineering, McGill University
The engineering issues that an analog and mixed-signal IC test engineer face are identical to those encountered by a system’s design engineer. Moreover, the test engineer often does not see his or her job activity as one that involves design, as they work without structured design flows or test-specific CAD tools. As a result, they often lack insight into what successful design engineers all know, that is, a circuit or system must implement some form of negative feedback to be robust, time-invariant and accurate. This talk looked at the shortcomings of some of the most popular techniques used by the analog test engineer to enhance their test such as load board circuits, loop-back and the golden-device approach, and other DFT techniques such as BIST, and use the negative feedback principle to highlight the path forward.