Intl Test Conference: Privacy

Significant Papers from the Past 35 Years

Many important papers have been presented at ITC over the past 35 years. Below is a selection of some of the most significant.

Our criteria for choosing the papers was:

Significance. The paper was highly significant at the time it was first presented. The paper influenced a concept in test.
Relevance. The paper, though old, is still extremely relevant to work today.
Historical Interest. The paper was the first or early report on a new standard or new concept.

The choice of significant papers was subjective. We nominated many additional significant papers for which there was no room.

The papers are sorted in two ways:

By Year
By Topic

Each presentation has an associated blurb to put it into context.

The 35 Year Significant Paper Selection Committee
Tony Ambler, University of Texas, Austin
Ken Butler, Texas Instruments
Scott Davidson, Sun Microsystems
Jerry Soden, Sandia National Labs
With Assistance From
Ben Bennetts, Bennetts Associates
Gordon Roberts, McGill University
Gordon Robinson
Burnie West, Credence Papers by Publication Year. 1979 Built-in Logic Block Observation Techniques, Bernd Koenemann, Joachim Mucha and Gunther Zwiehoff. Introduction Paper 1981 CMOS is Most Testable , M. W. Levi Introduction Paper 1983 New Techniques for High-Speed Analog Testing, Matthew Mahoney. Introduction Paper 1985 Model for Delay Faults Based Upon Paths, Gordon L. Smith. Introduction Paper 1987 Intel's Test Quality System, A. Thakar, Hector Sucar, and Pat Gelsinger Introduction Paper Interconnect Testing with Boundary Scan, Paul T. Wagner. Introduction Paper 1988 Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis, F. Joel Ferguson and John P. Shen Introduction Paper Membrane Probe-Card Technology (The Future for High-Performance Wafer Test), Brian Leslie and Farid Matta Introduction Paper 1989 Low-Cost Testing of High-Density Logic Components, R. W. Bassett, B. J. Butkus, S. L. Dingle, M. R. Faucher, P. S. Gillis, J. H. Panner, J. G. Petrovick, D. L. Wheater. Introduction Paper CMOS IC Stuck-Open-Fault Electrical Effects and Design Considerations., J. M. Soden, R. K. Treece, M. R. Taylor, C. F. Hawkins Introduction Paper 1990 ATPG for Ultra-Large Structured Designs, J. Waicukauski, P. Shupe, D. Giramma and A. Matin Introduction Paper Sequencer-per-Pin Test System Architecture, B. West and T. Napier Introduction Paper A Language for Describing Boundary-Scan Devices, K. Parker and S. Oresjo Introduction Paper 1991 The Effect of Different Test Sets on Quality Level Prediction: When is 80% Better Than 90%?, P. C. Maxwell, R. C. Aitken, V. Johansen and I Chiang. Introduction Paper 1992 DelayTest: The Next Frontier for LSSD Test Systems, B. Koenemann, J. Barlow, P. Chang, E. Gabrielson, C. Goertz, B. Keller, K. McCauley, J. Tischer, V. Iyengar, B. Rosen and T. Williams Introduction Paper ScanBIST: A Multifrequency Scan-based BIST Method, B. Nadeau Dostie, D. Burek and A. Hassan, Introduction Paper 1993 Structure and Metrology for an Analog Testability Bus, K. Parker, J. McDermid and S. Oresjo Introduction Paper A BIST Scheme for an SNR Test of a Sigma-Delta ADC, M. Toner and G. Roberts Introduction Paper 1994 QTAG: A Standard for Test Fixture-based I_DDQ/I_SSQ Monitors, K. Baker Introduction Paper Defect Classes: An Overdue Paradigm for CMOS IC Testing, C. Hawkins, J. Soden, A. Righter and F. Ferguson, Introduction Paper 1995 An Experimental Chip to Evaluate Test Techniques: Experiment Results, S. Ma, P. Franco and E. J. McCluskey. Introduction Paper Improved Boundary-Scan Design, L. Whetsel. Introduction Paper 1996 STIL: A New Language for Patterns and Waveforms, T. Taylor and G. Maston. Introduction Paper I_DDQ Test: Sensitivity Analysis of Scaling, T. Williams, R. Dennard, R. Kapur, M. R. Mercer and W. Maly. Introduction Paper Weak-Write Test Mode: An SRAM Cell Stability Design-for-Test Technique, A Meixner and J. Banik. Introduction Paper 1997 Current Signatures: Application, A. Gattiker and W. Maly. Introduction Paper 1998 Test Generation in VLSI Circuits for Crosstalk Noise, W. Chen, M. Breuer and S. Gupta. Introduction Paper High-Volume Microprocessor Test Escapes: An Analysis of Defects our Tests are Missing, W. Needham, C. Prunty and E. H. Yeoh. Introduction Paper Failure Analysis of Timing and I_DDQ-only Fails from the Sematech Test Methods Experiment, P. Nigh, D. Vallett, J. Wright, F. Motika, D. Forlenza, R. Kurtulik and W. Chong. Introduction Paper 1999 Logic BIST for Large Industrial Designs: Real Issues and Case Studies, G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan and J. Rajski. Introduction Paper Current Ratios: A Self-Scaling Technique for Production I_DDQ Testing, P. Maxwell, P. O'Neill, R. Aitken, R. Dudley, N. Jaarsma M. Quach and D. Wiseman. Introduction Paper 2000 Variance Reduction Using Wafer Patterns in I_DDQ Data, W. R.Daasch, J. McNames, D. Bockelman, K. Cota and R. Madge. Introduction Paper Test Method Evaluation Experiments and Data, P. Nigh and A. Gattiker. Introduction Paper Stuck-Fault Tests vs. Actual Defects, E. J. McCluskey and C. W. Tseng. Introduction Paper Wrapper Design for Embedded Core Test, E. J. Marinissen, S. K. Goel and M. Lousberg. Introduction Paper The Testability Features of the MCF5407 Containing the 4th Generation Coldfire Microprocessor Core , T. McLaurin and F. Frederick. Introduction Paper 2001 Neighbor Selection for Variance Reduction in I_DDQ and Other Parametric Data , W. Daasch, K. Cota, H. McNames and R. Madge. Introduction Paper Too Much Delay-Fault Coverage is a Bad Thing, J. Rearick. Introduction Paper OPMISR: The Foundation for Compressed ATPG Vectors, B. Keller, C. Barnhart and B. Koenemann Introduction Paper 2002 Embedded Deterministic Test for Low-Cost Manufacturing Test, J. Tyszer, J. Rajski, M. Kassab, A. Hertwig, N. Tamarapalli, N. Mukherjee, R. Thompson, G. Mrugalski, G. Eide, K. Tsai and J. Qian. Introduction Paper Papers by Topic. ATE Membrane Probe-Card Technology (The Future for High-Performance Wafer Test), Brian Leslie and Farid Matta Introduction Paper Low-Cost Testing of High-Density Logic Components, R. W. Bassett, B. J. Butkus, S. L. Dingle, M. R. Faucher, P. S. Gillis, J. H. Panner, J. G. Petrovick, D. L. Wheater. Introduction Paper Sequencer-per-Pin Test System Architecture, B. West and T. Napier Introduction Paper STIL: A New Language for Patterns and Waveforms, T. Taylor and G. Maston. Introduction Paper Automatic Test Pattern Generation (ATPG) ATPG for Ultra-Large Structured Designs, J. Waicukauski, P. Shupe, D. Giramma and A. Matin Introduction Paper DelayTest: The Next Frontier for LSSD Test Systems, B. Koenemann, J. Barlow, P. Chang, E. Gabrielson, C. Goertz, B. Keller, K. McCauley, J. Tischer, V. Iyengar, B. Rosen and T. Williams Introduction Paper Test Generation in VLSI Circuits for Crosstalk Noise, W. Chen, M. Breuer and S. Gupta. Introduction Paper Too Much Delay-Fault Coverage is a Bad Thing, J. Rearick. Introduction Paper Board and System Test Interconnect Testing with Boundary Scan, Paul T. Wagner. Introduction Paper A Language for Describing Boundary-Scan Devices, K. Parker and S. Oresjo Introduction Paper Improved Boundary-Scan Design, L. Whetsel. Introduction Paper DFT/BIST Built-in Logic Block Observation Techniques,Bernd Koenemann, Joachim Mucha and Gunther Zwiehoff. Introduction Paper ScanBIST: A Multifrequency Scan-based BIST Method, B. Nadeau Dostie, D. Burek and A. Hassan, Introduction Paper Logic BIST for Large Industrial Designs: Real Issues and Case Studies, G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan and J. Rajski. Introduction Paper OPMISR: The Foundation for Compressed ATPG Vectors, B. Keller, C. Barnhart and B. Koenemann Introduction Paper Embedded Deterministic Test for Low-Cost Manufacturing Test, J. Tyszer, J. Rajski, M. Kassab, A. Hertwig, N. Tamarapalli, N. Mukherjee, R. Thompson, G. Mrugalski, G. Eide, K. Tsai and J. Qian. Introduction Paper Diagnosis/Fault Models Model for Delay Faults Based Upon Paths, Gordon L. Smith. Introduction Paper Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis, F. Joel Ferguson and John P. Shen Introduction Paper Defect Classes: An Overdue Paradigm for CMOS IC Testing, C. Hawkins, J. Soden, A. Righter and F. Ferguson, Introduction Paper IDDQ Testing CMOS is Most Testable , M. W. Levi Introduction Paper CMOS IC Stuck-Open-Fault Electrical Effects and Design Considerations., J. M. Soden, R. K. Treece, M. R. Taylor, C. F. Hawkins Introduction Paper QTAG: A Standard for Test Fixture-based I_DDQ/I_SSQ Monitors, K. Baker Introduction Paper I_DDQ Test: Sensitivity Analysis of Scaling, T. Williams, R. Kapur, M. R. Mercer, W. Maly. Introduction Paper Current Signatures: Application, A. Gattiker and W. Maly. Introduction Paper Current Ratios: A Self-Scaling Technique for Production I_DDQ Testing, P. Maxwell, P. O'Neill, R. Aitken, R. Dudley, N. Jaarsma M. Quach and D. Wiseman. Introduction Paper Variance Reduction Using Wafer Patterns in I_DDQ Data, W. R.Daasch, J. McNames, D. Bockelman, K. Cota and R. Madge. Introduction Paper Neighbor Selection for Variance Reduction in I_DDQ and Other Parametric Data , W. Daasch, K. Cota, H. McNames and R. Madge. Introduction Paper Memory Test Weak-Write Test Mode: An SRAM Cell Stability Design-for-Test Technique, A Meixner, J. Banik. Introduction Paper Microprocessor Test Intel's Test Quality System, A. Thakar, Hector Sucar, and Pat Gelsinger Introduction Paper High-Volume Microprocessor Test Escapes: An Analysis of Defects our Tests are Missing, W. Needham, C. Prunty and E. H. Yeoh. Introduction Paper The Testability Features of the MCF5407 Containing the 4th Generation Coldfire Microprocessor Core , T. McLaurin and F. Frederick. Introduction Paper Mixed Signal Test New Techniques for High-Speed Analog Testing, Matthew Mahoney. Introduction Paper Structure and Metrology for an Analog Testability Bus, K. Parker, J. McDermid and S. Oresjo Introduction Paper A BIST Scheme for an SNR Test of a Sigma-Delta ADC, M. Toner and G. Roberts Introduction Paper System on Chip Test Wrapper Design for Embedded Core Test, E. J. Marinissen, S. K. Goel and M. Lousberg. Introduction Paper Test Methods The Effect of Different Test Sets on Quality Level Prediction: When is 80% Better Than 90%?, P. C. Maxwell, R. C. Aitken, V. Johansen and I Chiang. Introduction Paper An Experimental Chip to Evaluate Test Techniques: Experiment Results, S. Ma, P. Franco, E. McCluskey. Introduction Paper Failure Analysis of Timing and I_DDQ-only Fails from the Sematech Test Methods Experiment, P. Nigh, D. Vallett, J. Wright, F. Motika, D. Forlenza, R. Kurtulik and W. Chong. Introduction Paper Test Method Evaluation Experiments and Data, P. Nigh and A. Gattiker. Introduction Paper Stuck-Fault Tests vs. Actual Defects, E. J. McCluskey and C. W. Tseng. Introduction Paper Please send comments and suggestions to Jerry Soden

Significant Papers from the Past 35 Years

Papers by Publication Year.

Papers by Topic.