More Information PDF version of the 2007 Call for Papers

Call for Papers - 2007

Facing Nanometer-Technology Test Challenges

October 23 - 25, 2007
Santa Clara Convention Center
Santa Clara, CA, USA

(Test Week™ is October 21-26, 2007)

International Test Conference is the world's premier conference dedicated to the electronic test of devices, boards and systems—covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

ITC, the cornerstone of the Test Week™ event, offers a wide variety of technical activities targeted at test and design theoreticians and practitioners, including formal paper sessions, tutorials, panel sessions, case studies, lecture and application series, commercial exhibits and presentations, and a host of ancillary professional meetings.

Conference Theme
This year ITC will focus on refined as well as breakthrough test technologies for nanometer-technology designs. What innovative test methods are you working on that will fundamentally address the nanometer-technology challenges such as quality and cost of test? ITC invites submissions on the latest techniques for testing and diagnosing ICs, boards and systems.

Conference Focus Topics

• Adaptive Test
• BIST or Embedded Test-Chip and Board
• Bring-up Test and Debug
• Design and Test for Reliability
• Experiments and Case Studies
• High-Speed I/O Test
• High-Speed Digital Test
• Low-Cost Test/ATE
• On-Chip Test Compression
• RF Testing
• Test Data Analysis
• Test and Design for Manufacturability
• Test for Nanometer Technologies
• Test Resource Partitioning

Hot Topics

• Board and System Test
• Defect-based Testing
• Innovative Industrial Test Practices
• On-line Test
• Power Issues in Test
• Volume Diagnosis and Yield Learning

Regular Topics

• ATE Hardware and Software
• ATPG, Test Synthesis
• Boundary-Scan
• Design-for-Test: Chip, Board, System
• Economics of Test
• FPGA Test
• IDDQ and Current Test
• Interface Issues
• Loadboard Design and Simulation
• MCM and KGD Test
• Memory Test
• Microprocessor Test
• Mixed-Signal and Analog Test
• Multisite Testt
• Production Test Automation
• System-on-Chip Test
• System-in-Package Test
• Test Standards
• Test Effectiveness
• Wafer Probe

The 2007 conference year will focus on breakthrough ideas to address the challenges of providing high-quality, cost-effective tests for nanometer-technology designs. Authors are invited to submit original, unpublished papers describing recent work in the field of test and design. Submissions simultaneously under review or accepted by another conference, symposium or journal will be rejected. ITC will work cooperatively with others to check for double submissions.

Submissions must include:

• Title of paper.
• Name, affiliation, mailing address, e-mail address, phone and fax number of each author.
• Designation of the presenter(s). ITC will communicate with the presenter.
• One or two topic(s) from the topic list, or a description of your topic.
• An electronic copy of a complete paper of 10 pages maximum, or an extended summary of from four to six pages. Submissions of less than four pages are rarely accepted.
• An abstract of 35 words or less.

ITC maintains a highly competitive selection process for papers presented. For details of the selection process, please consult our Web site. Submissions must clearly describe the status of the reported work, its significance and highlights. Supporting data, results and conclusions, and references to prior work must also be included. ITC does not accept submissions that do not meet all specified criteria. Please note that the submission deadline is firm.

• Submission Deadline: February 16, 2007
• Author Notification: May 25, 2007
• Manuscript Deadline: July 6, 2007

Proposals for panels and lecture or application series are also welcome. All submissions and presentations must be in electronic format. Prospective authors should read the detailed instructions regarding formats and submission requirements that are available on the ITC Program Web site.

Test Week Tutorial and workshop proposals are also welcomed. Deadlines and other information about proposals about proposals can be obtained from TTTC.

For further information, check the ITC Web page or contact:

International Test Conference
Washington, DC, USA
Tel: +1 202.973.8665 Fax: +1 202.331.0111
E-mail: itc@courtesyassoc.com

Program Chair
Janusz Rajski, Mentor Graphics Corporation
E-mail: janusz_rajski@mentor.com